Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <common/debug.h> |
| 10 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 11 | #include "../qos_common.h" |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 12 | #include "../qos_reg.h" |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 13 | #include "qos_init_h3_v10.h" |
| 14 | |
| 15 | #define RCAR_QOS_VERSION "rev.0.36" |
| 16 | |
Marek Vasut | 436bd7a | 2019-06-14 01:25:01 +0200 | [diff] [blame] | 17 | #include "qos_init_h3_v10_mstat.h" |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 18 | |
| 19 | void qos_init_h3_v10(void) |
| 20 | { |
| 21 | /* DRAM Split Address mapping */ |
| 22 | #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \ |
| 23 | (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO) |
| 24 | NOTICE("BL2: DRAM Split is 4ch\n"); |
| 25 | io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT |
| 26 | | ADSPLCR0_SPLITSEL(0xFFU) |
| 27 | | ADSPLCR0_AREA(0x1BU) |
| 28 | | ADSPLCR0_SWP); |
| 29 | io_write_32(AXI_ADSPLCR1, 0x00000000U); |
| 30 | io_write_32(AXI_ADSPLCR2, 0xA8A90000U); |
| 31 | io_write_32(AXI_ADSPLCR3, 0x00000000U); |
| 32 | #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH |
| 33 | NOTICE("BL2: DRAM Split is 2ch\n"); |
| 34 | io_write_32(AXI_ADSPLCR0, 0x00000000U); |
| 35 | io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
| 36 | | ADSPLCR0_SPLITSEL(0xFFU) |
| 37 | | ADSPLCR0_AREA(0x1BU) |
| 38 | | ADSPLCR0_SWP); |
| 39 | io_write_32(AXI_ADSPLCR2, 0x00000000U); |
| 40 | io_write_32(AXI_ADSPLCR3, 0x00000000U); |
| 41 | #else |
| 42 | NOTICE("BL2: DRAM Split is OFF\n"); |
| 43 | #endif |
| 44 | |
| 45 | #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) |
| 46 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 47 | NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); |
| 48 | #endif |
| 49 | |
| 50 | /* AR Cache setting */ |
| 51 | io_write_32(0xE67D1000U, 0x00000100U); |
| 52 | io_write_32(0xE67D1008U, 0x00000100U); |
| 53 | |
| 54 | /* Resource Alloc setting */ |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 55 | io_write_32(QOSCTRL_RAS, 0x00000040U); |
| 56 | io_write_32(QOSCTRL_FIXTH, 0x000F0005U); |
| 57 | io_write_32(QOSCTRL_REGGD, 0x00000004U); |
| 58 | io_write_64(QOSCTRL_DANN, 0x0202000004040404UL); |
| 59 | io_write_32(QOSCTRL_DANT, 0x003C1110U); |
| 60 | io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */ |
| 61 | io_write_64(QOSCTRL_EMS, 0x0000000000000000UL); |
| 62 | io_write_32(QOSCTRL_INSFC, 0xC7840001U); |
| 63 | io_write_32(QOSCTRL_BERR, 0x00000000U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 64 | |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 65 | /* QOSBW setting */ |
| 66 | io_write_32(QOSCTRL_SL_INIT, |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 67 | SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK); |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 68 | io_write_32(QOSCTRL_REF_ARS, 0x00330000U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 69 | |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 70 | /* QOSBW SRAM setting */ |
Marek Vasut | 32ccc2c | 2019-06-14 01:27:27 +0200 | [diff] [blame^] | 71 | uint32_t i; |
| 72 | |
| 73 | for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { |
| 74 | io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); |
| 75 | io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 76 | } |
Marek Vasut | 32ccc2c | 2019-06-14 01:27:27 +0200 | [diff] [blame^] | 77 | for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { |
| 78 | io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); |
| 79 | io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 80 | } |
| 81 | |
| 82 | /* 3DG bus Leaf setting */ |
| 83 | io_write_32(0xFD820808U, 0x00001234U); |
| 84 | io_write_32(0xFD820800U, 0x0000003FU); |
| 85 | io_write_32(0xFD821800U, 0x0000003FU); |
| 86 | io_write_32(0xFD822800U, 0x0000003FU); |
| 87 | io_write_32(0xFD823800U, 0x0000003FU); |
| 88 | io_write_32(0xFD824800U, 0x0000003FU); |
| 89 | io_write_32(0xFD825800U, 0x0000003FU); |
| 90 | io_write_32(0xFD826800U, 0x0000003FU); |
| 91 | io_write_32(0xFD827800U, 0x0000003FU); |
| 92 | |
| 93 | /* Resource Alloc start */ |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 94 | io_write_32(QOSCTRL_RAEN, 0x00000001U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 95 | |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 96 | /* QOSBW start */ |
| 97 | io_write_32(QOSCTRL_STATQC, 0x00000001U); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 98 | #else |
| 99 | NOTICE("BL2: QoS is None\n"); |
| 100 | |
| 101 | /* Resource Alloc setting */ |
Marek Vasut | b0eb988 | 2019-06-14 01:22:38 +0200 | [diff] [blame] | 102 | io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 103 | #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ |
| 104 | } |