Chris Kay | 03be39d | 2021-05-05 13:38:30 +0100 | [diff] [blame] | 1 | Maximum Power Mitigation Mechanism (MPMM) Bindings |
| 2 | ================================================== |
| 3 | |
| 4 | |MPMM| support cannot be determined at runtime by the firmware. Instead, these |
| 5 | DTB bindings allow the platform to communicate per-core support for |MPMM| via |
| 6 | the ``HW_CONFIG`` device tree blob. |
| 7 | |
| 8 | Bindings |
| 9 | ^^^^^^^^ |
| 10 | |
| 11 | .. contents:: |
| 12 | :local: |
| 13 | |
| 14 | ``/cpus/cpus/cpu*`` node properties |
| 15 | """"""""""""""""""""""""""""""""""" |
| 16 | |
| 17 | The ``cpu`` node has been augmented to allow the platform to indicate support |
| 18 | for |MPMM| on a given core. |
| 19 | |
| 20 | +-------------------+-------+-------------+------------------------------------+ |
| 21 | | Property name | Usage | Value type | Description | |
| 22 | +===================+=======+=============+====================================+ |
| 23 | | ``supports-mpmm`` | O | ``<empty>`` | If present, indicates that |MPMM| | |
| 24 | | | | | is available on this core. | |
| 25 | +-------------------+-------+-------------+------------------------------------+ |
| 26 | |
| 27 | Example |
| 28 | ^^^^^^^ |
| 29 | |
| 30 | An example system offering two cores, one with support for |MPMM| and one |
| 31 | without, can be described as follows: |
| 32 | |
| 33 | .. code-block:: |
| 34 | |
| 35 | cpus { |
| 36 | #address-cells = <2>; |
| 37 | #size-cells = <0>; |
| 38 | |
| 39 | cpu0@00000 { |
| 40 | ... |
| 41 | |
| 42 | supports-mpmm; |
| 43 | }; |
| 44 | |
| 45 | cpu1@00100 { |
| 46 | ... |
| 47 | }; |
| 48 | } |