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git01.mediatek.com / filogic / atf / 32409c7ae96f514056144ce9941798c92a243674 / . / plat / xilinx / versal / pm_service / pm_node.h
blob: 1b82ec70de18a563605672f72a9154413c06de40 [file] [log] [blame]
Tejas Patel354fe572018-12-14 00:55:37 -0800[diff] [blame]1/*
2 * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/* Versal PM nodes enums and defines */
8
9#ifndef PM_NODE_H
10#define PM_NODE_H
11
12/*********************************************************************
13 * Macro definitions
14 ********************************************************************/
15
16#define NODE_CLASS_SHIFT 26U
17#define NODE_SUBCLASS_SHIFT 20U
18#define NODE_TYPE_SHIFT 14U
19#define NODE_INDEX_SHIFT 0U
20#define NODE_CLASS_MASK_BITS 0x3F
21#define NODE_SUBCLASS_MASK_BITS 0x3F
22#define NODE_TYPE_MASK_BITS 0x3F
23#define NODE_INDEX_MASK_BITS 0x3FFF
24#define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT)
25#define NODE_SUBCLASS_MASK (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT)
26#define NODE_TYPE_MASK (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT)
27#define NODE_INDEX_MASK (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT)
28
29#define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \
30 ((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \
31 (((SUBCLASS) & NODE_SUBCLASS_MASK_BITS) << NODE_SUBCLASS_SHIFT) | \
32 (((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \
33 (((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT))
34
35#define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT)
36#define NODESUBCLASS(ID) (((ID) & NODE_SUBCLASS_MASK) >> \
37 NODE_SUBCLASS_SHIFT)
38#define NODETYPE(ID) (((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT)
39#define NODEINDEX(ID) (((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT)
40
41/*********************************************************************
42 * Enum definitions
43 ********************************************************************/
44
45/* Node class types */
46enum pm_node_class {
47 XPM_NODECLASS_MIN,
48
49 XPM_NODECLASS_POWER,
50 XPM_NODECLASS_CLOCK,
51 XPM_NODECLASS_RESET,
52 XPM_NODECLASS_MEMIC,
53 XPM_NODECLASS_STMIC,
54 XPM_NODECLASS_DEVICE,
55
56 XPM_NODECLASS_MAX
57};
58
59enum pm_device_node_subclass {
60 /* Device types */
61 XPM_NODESUBCL_DEV_CORE = 1,
62 XPM_NODESUBCL_DEV_PERIPH,
63 XPM_NODESUBCL_DEV_MEM,
64 XPM_NODESUBCL_DEV_SOC,
65 XPM_NODESUBCL_DEV_MEM_CTRLR,
66 XPM_NODESUBCL_DEV_PHY,
67};
68
69enum pm_device_node_type {
70 /* Device types */
71 XPM_NODETYPE_DEV_CORE_PMC = 1,
72 XPM_NODETYPE_DEV_CORE_PSM,
73 XPM_NODETYPE_DEV_CORE_APU,
74 XPM_NODETYPE_DEV_CORE_RPU,
75 XPM_NODETYPE_DEV_OCM,
76 XPM_NODETYPE_DEV_TCM,
77 XPM_NODETYPE_DEV_L2CACHE,
78 XPM_NODETYPE_DEV_DDR,
79 XPM_NODETYPE_DEV_PERIPH,
80 XPM_NODETYPE_DEV_SOC,
81 XPM_NODETYPE_DEV_GT,
82};
83
84/* Device node Indexes */
85enum pm_device_node_idx {
86 /* Device nodes */
87 XPM_NODEIDX_DEV_MIN,
88
89 /* Processor devices */
90 XPM_NODEIDX_DEV_PMC_PROC,
91 XPM_NODEIDX_DEV_PSM_PROC,
92 XPM_NODEIDX_DEV_ACPU_0,
93 XPM_NODEIDX_DEV_ACPU_1,
94 XPM_NODEIDX_DEV_RPU0_0,
95 XPM_NODEIDX_DEV_RPU0_1,
96
97 /* Memory devices */
98 XPM_NODEIDX_DEV_OCM_0,
99 XPM_NODEIDX_DEV_OCM_1,
100 XPM_NODEIDX_DEV_OCM_2,
101 XPM_NODEIDX_DEV_OCM_3,
102 XPM_NODEIDX_DEV_TCM_0_A,
103 XPM_NODEIDX_DEV_TCM_0_B,
104 XPM_NODEIDX_DEV_TCM_1_A,
105 XPM_NODEIDX_DEV_TCM_1_B,
106 XPM_NODEIDX_DEV_L2_BANK_0,
107 XPM_NODEIDX_DEV_DDR_0,
108 XPM_NODEIDX_DEV_DDR_1,
109 XPM_NODEIDX_DEV_DDR_2,
110 XPM_NODEIDX_DEV_DDR_3,
111 XPM_NODEIDX_DEV_DDR_4,
112 XPM_NODEIDX_DEV_DDR_5,
113 XPM_NODEIDX_DEV_DDR_6,
114 XPM_NODEIDX_DEV_DDR_7,
115
116 /* LPD Peripheral devices */
117 XPM_NODEIDX_DEV_USB_0,
118 XPM_NODEIDX_DEV_GEM_0,
119 XPM_NODEIDX_DEV_GEM_1,
120 XPM_NODEIDX_DEV_SPI_0,
121 XPM_NODEIDX_DEV_SPI_1,
122 XPM_NODEIDX_DEV_I2C_0,
123 XPM_NODEIDX_DEV_I2C_1,
124 XPM_NODEIDX_DEV_CAN_FD_0,
125 XPM_NODEIDX_DEV_CAN_FD_1,
126 XPM_NODEIDX_DEV_UART_0,
127 XPM_NODEIDX_DEV_UART_1,
128 XPM_NODEIDX_DEV_GPIO,
129 XPM_NODEIDX_DEV_TTC_0,
130 XPM_NODEIDX_DEV_TTC_1,
131 XPM_NODEIDX_DEV_TTC_2,
132 XPM_NODEIDX_DEV_TTC_3,
133 XPM_NODEIDX_DEV_SWDT_LPD,
134
135 /* FPD Peripheral devices */
136 XPM_NODEIDX_DEV_SWDT_FPD,
137
138 /* PMC Peripheral devices */
139 XPM_NODEIDX_DEV_OSPI,
140 XPM_NODEIDX_DEV_QSPI,
141 XPM_NODEIDX_DEV_GPIO_PMC,
142 XPM_NODEIDX_DEV_I2C_PMC,
143 XPM_NODEIDX_DEV_SDIO_0,
144 XPM_NODEIDX_DEV_SDIO_1,
145
146 XPM_NODEIDX_DEV_PL_0,
147 XPM_NODEIDX_DEV_PL_1,
148 XPM_NODEIDX_DEV_PL_2,
149 XPM_NODEIDX_DEV_PL_3,
150 XPM_NODEIDX_DEV_RTC,
151 XPM_NODEIDX_DEV_ADMA_0,
152 XPM_NODEIDX_DEV_ADMA_1,
153 XPM_NODEIDX_DEV_ADMA_2,
154 XPM_NODEIDX_DEV_ADMA_3,
155 XPM_NODEIDX_DEV_ADMA_4,
156 XPM_NODEIDX_DEV_ADMA_5,
157 XPM_NODEIDX_DEV_ADMA_6,
158 XPM_NODEIDX_DEV_ADMA_7,
159 XPM_NODEIDX_DEV_IPI_0,
160 XPM_NODEIDX_DEV_IPI_1,
161 XPM_NODEIDX_DEV_IPI_2,
162 XPM_NODEIDX_DEV_IPI_3,
163 XPM_NODEIDX_DEV_IPI_4,
164 XPM_NODEIDX_DEV_IPI_5,
165 XPM_NODEIDX_DEV_IPI_6,
166
167 /* Entire SoC */
168 XPM_NODEIDX_DEV_SOC,
169
170 /* DDR memory controllers */
171 XPM_NODEIDX_DEV_DDRMC_0,
172 XPM_NODEIDX_DEV_DDRMC_1,
173 XPM_NODEIDX_DEV_DDRMC_2,
174 XPM_NODEIDX_DEV_DDRMC_3,
175
176 /* GT devices */
177 XPM_NODEIDX_DEV_GT_0,
178 XPM_NODEIDX_DEV_GT_1,
179 XPM_NODEIDX_DEV_GT_2,
180 XPM_NODEIDX_DEV_GT_3,
181 XPM_NODEIDX_DEV_GT_4,
182 XPM_NODEIDX_DEV_GT_5,
183 XPM_NODEIDX_DEV_GT_6,
184 XPM_NODEIDX_DEV_GT_7,
185 XPM_NODEIDX_DEV_GT_8,
186 XPM_NODEIDX_DEV_GT_9,
187 XPM_NODEIDX_DEV_GT_10,
188
189 XPM_NODEIDX_DEV_MAX
190};
191
192#endif /* PM_NODE_H */