Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
| 10 | #include <common/bl_common.h> |
| 11 | #include <context.h> |
| 12 | #include <lib/el3_runtime/context_mgmt.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <denver.h> |
| 15 | #include <mce.h> |
| 16 | #include <mce_private.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 17 | #include <platform_def.h> |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 18 | #include <stdbool.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 19 | #include <string.h> |
| 20 | #include <errno.h> |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 21 | #include <t194_nvg.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 22 | #include <tegra_def.h> |
| 23 | #include <tegra_platform.h> |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 24 | #include <tegra_private.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 25 | |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 26 | /* Handler to check if MCE firmware is supported */ |
| 27 | static bool mce_firmware_not_supported(void) |
| 28 | { |
| 29 | bool status; |
| 30 | |
| 31 | /* these platforms do not load MCE firmware */ |
| 32 | status = tegra_platform_is_linsim() || tegra_platform_is_qt() || |
| 33 | tegra_platform_is_virt_dev_kit(); |
| 34 | |
| 35 | return status; |
| 36 | } |
| 37 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 38 | /******************************************************************************* |
| 39 | * Common handler for all MCE commands |
| 40 | ******************************************************************************/ |
Anthony Zhou | 5e890b3 | 2017-04-28 13:52:58 +0800 | [diff] [blame] | 41 | int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 42 | uint64_t arg2) |
| 43 | { |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 44 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 45 | |
| 46 | switch (cmd) { |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 47 | case (uint64_t)MCE_CMD_ENTER_CSTATE: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 48 | ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1); |
| 49 | if (ret < 0) { |
| 50 | ERROR("%s: enter_cstate failed(%d)\n", __func__, ret); |
| 51 | } |
| 52 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 53 | break; |
| 54 | |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 55 | case (uint64_t)MCE_CMD_IS_SC7_ALLOWED: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 56 | ret = nvg_is_sc7_allowed(); |
| 57 | if (ret < 0) { |
| 58 | ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret); |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 59 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 60 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 61 | break; |
| 62 | |
Anthony Zhou | c46150f | 2017-09-20 17:18:56 +0800 | [diff] [blame] | 63 | case (uint64_t)MCE_CMD_ONLINE_CORE: |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 64 | ret = nvg_online_core((uint32_t)arg0); |
| 65 | if (ret < 0) { |
| 66 | ERROR("%s: online_core failed(%d)\n", __func__, ret); |
| 67 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 68 | |
| 69 | break; |
| 70 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 71 | default: |
Anthony Zhou | 5e890b3 | 2017-04-28 13:52:58 +0800 | [diff] [blame] | 72 | ERROR("unknown MCE command (%llu)\n", cmd); |
Varun Wadekar | 7aa6c03 | 2017-10-19 12:02:17 -0700 | [diff] [blame] | 73 | ret = -EINVAL; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 74 | break; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | return ret; |
| 78 | } |
| 79 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 80 | /******************************************************************************* |
| 81 | * Handler to update carveout values for Video Memory Carveout region |
| 82 | ******************************************************************************/ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 83 | int32_t mce_update_gsc_videomem(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 84 | { |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 85 | int32_t ret; |
| 86 | |
| 87 | /* |
| 88 | * MCE firmware is not running on simulation platforms. |
| 89 | */ |
| 90 | if (mce_firmware_not_supported()) { |
| 91 | ret = -EINVAL; |
| 92 | } else { |
| 93 | ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR); |
| 94 | } |
| 95 | |
| 96 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | /******************************************************************************* |
| 100 | * Handler to update carveout values for TZDRAM aperture |
| 101 | ******************************************************************************/ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 102 | int32_t mce_update_gsc_tzdram(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 103 | { |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 104 | int32_t ret; |
| 105 | |
| 106 | /* |
| 107 | * MCE firmware is not running on simulation platforms. |
| 108 | */ |
| 109 | if (mce_firmware_not_supported()) { |
| 110 | ret = -EINVAL; |
| 111 | } else { |
| 112 | ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM); |
| 113 | } |
| 114 | |
| 115 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | /******************************************************************************* |
| 119 | * Handler to update carveout values for TZ SysRAM aperture |
| 120 | ******************************************************************************/ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 121 | int32_t mce_update_gsc_tzram(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 122 | { |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 123 | int32_t ret; |
| 124 | |
| 125 | /* |
| 126 | * MCE firmware is not running on simulation platforms. |
| 127 | */ |
| 128 | if (mce_firmware_not_supported()) { |
| 129 | ret = -EINVAL; |
| 130 | } else { |
| 131 | ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM); |
| 132 | } |
| 133 | |
| 134 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 138 | * Handler to issue the UPDATE_CSTATE_INFO request |
| 139 | ******************************************************************************/ |
Anthony Zhou | 5e890b3 | 2017-04-28 13:52:58 +0800 | [diff] [blame] | 140 | void mce_update_cstate_info(const mce_cstate_info_t *cstate) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 141 | { |
| 142 | /* issue the UPDATE_CSTATE_INFO request */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 143 | nvg_update_cstate_info(cstate->cluster, cstate->ccplex, cstate->system, |
| 144 | cstate->wake_mask, cstate->update_wake_mask); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | /******************************************************************************* |
| 148 | * Handler to read the MCE firmware version and check if it is compatible |
| 149 | * with interface header the BL3-1 was compiled against |
| 150 | ******************************************************************************/ |
| 151 | void mce_verify_firmware_version(void) |
| 152 | { |
| 153 | uint64_t version; |
| 154 | uint32_t major, minor; |
| 155 | |
| 156 | /* |
| 157 | * MCE firmware is not running on simulation platforms. |
| 158 | */ |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 159 | if (mce_firmware_not_supported()) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 160 | return; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 161 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 162 | |
| 163 | /* |
| 164 | * Read the MCE firmware version and extract the major and minor |
| 165 | * version fields |
| 166 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 167 | version = nvg_get_version(); |
| 168 | minor = (uint32_t)version; |
| 169 | major = (uint32_t)(version >> 32); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 170 | |
Varun Wadekar | 093bfaa | 2017-11-07 08:50:55 -0800 | [diff] [blame] | 171 | INFO("MCE Version - HW=%u:%u, SW=%u:%u\n", major, minor, |
| 172 | TEGRA_NVG_VERSION_MAJOR, TEGRA_NVG_VERSION_MINOR); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 173 | |
| 174 | /* |
| 175 | * Verify that the MCE firmware version and the interface header |
| 176 | * match |
| 177 | */ |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 178 | if (major != (uint32_t)TEGRA_NVG_VERSION_MAJOR) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 179 | ERROR("MCE major version mismatch\n"); |
| 180 | panic(); |
| 181 | } |
| 182 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 183 | if (minor < (uint32_t)TEGRA_NVG_VERSION_MINOR) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 184 | ERROR("MCE minor version mismatch\n"); |
| 185 | panic(); |
| 186 | } |
| 187 | } |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 188 | |
| 189 | /******************************************************************************* |
| 190 | * Handler to enable the strict checking mode |
| 191 | ******************************************************************************/ |
| 192 | void mce_enable_strict_checking(void) |
| 193 | { |
| 194 | uint64_t sctlr = read_sctlr_el3(); |
| 195 | int32_t ret = 0; |
| 196 | |
| 197 | if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { |
| 198 | /* |
| 199 | * Step1: TZ-DRAM and TZRAM should be setup before the MMU is |
| 200 | * enabled. |
| 201 | * |
| 202 | * The common code makes sure that TZDRAM/TZRAM are already |
| 203 | * enabled before calling into this handler. If this is not the |
| 204 | * case, the following sequence must be executed before moving |
| 205 | * on to step 2. |
| 206 | * |
| 207 | * tlbialle1is(); |
| 208 | * tlbialle3is(); |
| 209 | * dsbsy(); |
| 210 | * isb(); |
| 211 | * |
| 212 | */ |
| 213 | if ((sctlr & (uint64_t)SCTLR_M_BIT) == (uint64_t)SCTLR_M_BIT) { |
| 214 | tlbialle1is(); |
| 215 | tlbialle3is(); |
| 216 | dsbsy(); |
| 217 | isb(); |
| 218 | } |
| 219 | |
| 220 | /* |
| 221 | * Step2: SCF flush - Clean and invalidate caches and clear the |
| 222 | * TR-bits |
| 223 | */ |
| 224 | ret = nvg_roc_clean_cache_trbits(); |
| 225 | if (ret < 0) { |
| 226 | ERROR("%s: flush cache_trbits failed(%d)\n", __func__, |
| 227 | ret); |
| 228 | return; |
| 229 | } |
| 230 | |
| 231 | /* |
| 232 | * Step3: Issue the SECURITY_CONFIG request to MCE to enable |
| 233 | * strict checking mode. |
| 234 | */ |
| 235 | nvg_enable_strict_checking_mode(); |
| 236 | } |
| 237 | } |