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git01.mediatek.com / filogic / atf / 31f0232da40ba7a10dcd1fb3059d3a21e74c05ab / . / plat / imx / common / include / imx_snvs.h
blob: 565c451dd804f1ac997b463b4f44bc583970ebe8 [file] [log] [blame]
Bryan O'Donoghue84cbb8d2018-06-25 13:15:10 +0100[diff] [blame]1/*
Samuel Hollande6c94952019-12-04 02:48:37 -0600[diff] [blame]2 * Copyright (C) 2018-2019, ARM Limited and Contributors. All rights reserved.
Bryan O'Donoghue84cbb8d2018-06-25 13:15:10 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]6#ifndef IMX_SNVS_H
7#define IMX_SNVS_H
Bryan O'Donoghue84cbb8d2018-06-25 13:15:10 +0100[diff] [blame]8
Samuel Hollande6c94952019-12-04 02:48:37 -0600[diff] [blame]9#include <cdefs.h>
Bryan O'Donoghue84cbb8d2018-06-25 13:15:10 +0100[diff] [blame]10#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]11
Bryan O'Donoghue84cbb8d2018-06-25 13:15:10 +0100[diff] [blame]12#include <arch.h>
13
14struct snvs {
15 uint32_t hplr;
16 uint32_t hpcomr;
17 uint32_t hpcr;
18 uint32_t hpsicr;
19 uint32_t hpsvcr;
20 uint32_t hpsr;
21 uint32_t hpsvsr;
22 uint32_t hphacivr;
23 uint32_t hphacr;
24 uint32_t hprtcmr;
25 uint32_t hprtclr;
26 uint32_t hptamr;
27 uint32_t hptalr;
28 uint32_t lplr;
29 uint32_t lpcr;
30 uint32_t lpmkcr;
31 uint32_t lpsvcr;
32 uint32_t lptgfcr;
33 uint32_t lptdcr;
34 uint32_t lpsr;
35 uint32_t lpsrtcmr;
36 uint32_t lpsrtclr;
37 uint32_t lptar;
38 uint32_t lpsmcmr;
39 uint32_t lpsmclr;
40 uint32_t lppgdr;
41 uint32_t lpgpr0_alias;
42 uint8_t lpzmkr[32];
43 uint16_t res0;
44 uint32_t lpgpr0[4];
45 uint32_t lptdc2r;
46 uint32_t lptdsr;
47 uint32_t lptgf1cr;
48 uint32_t lptgf2cr;
49 uint32_t res1[4];
50 uint32_t lpat1cr;
51 uint32_t lpat2cr;
52 uint32_t lpat3cr;
53 uint32_t lpat4cr;
54 uint32_t lpat5cr;
55 uint32_t res2[3];
56 uint32_t lpatctlr;
57 uint32_t lpatclkr;
58 uint32_t lpatrc1r;
59 uint32_t lpatrc2r;
60 uint32_t res3[706];
61 uint32_t hpvidr1;
62 uint32_t hpvidr2;
63} __packed;
64
65/* Define the HPCOMR bits */
66#define HPCOMR_NPSWA_EN BIT(31)
67#define HPCOMR_HAC_STOP BIT(19)
68#define HPCOMR_HAC_CLEAR BIT(18)
69#define HPCOMR_HAC_LOAD BIT(17)
70#define HPCOMR_HAC_EN BIT(16)
71#define HPCOMR_MKS_EN BIT(13)
72#define HPCOMR_PROG_ZMK BIT(12)
73#define HPCOMR_SW_LPSV BIT(10)
74#define HPCOMR_SW_FSV BIT(9)
75#define HPCOMR_SW_SV BIT(8)
76#define HPCOMR_LP_SWR_DIS BIT(5)
77#define HPCOMR_LP_SWR BIT(4)
78#define HPCOMR_SSM_SFNS_DIS BIT(2)
79#define HPCOMR_SSM_ST_DIS BIT(1)
80#define HPCOMR_SSM_ST BIT(0)
81
82void imx_snvs_init(void);
83
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]84#endif /* IMX_SNVS_H */