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Yann Gautier1e5e85a2018-07-03 18:32:12 +02001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef MMC_H
8#define MMC_H
Yann Gautier1e5e85a2018-07-03 18:32:12 +02009
10#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <lib/utils_def.h>
Yann Gautier1e5e85a2018-07-03 18:32:12 +020013
14#define MMC_BLOCK_SIZE U(512)
15#define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1))
16#define MMC_BOOT_CLK_RATE (400 * 1000)
17
18#define MMC_CMD(_x) U(_x)
19
20#define MMC_ACMD(_x) U(_x)
21
22#define OCR_POWERUP BIT(31)
23#define OCR_HCS BIT(30)
24#define OCR_BYTE_MODE (U(0) << 29)
25#define OCR_SECTOR_MODE (U(2) << 29)
26#define OCR_ACCESS_MODE_MASK (U(3) << 29)
27#define OCR_3_5_3_6 BIT(23)
28#define OCR_3_4_3_5 BIT(22)
29#define OCR_3_3_3_4 BIT(21)
30#define OCR_3_2_3_3 BIT(20)
31#define OCR_3_1_3_2 BIT(19)
32#define OCR_3_0_3_1 BIT(18)
33#define OCR_2_9_3_0 BIT(17)
34#define OCR_2_8_2_9 BIT(16)
35#define OCR_2_7_2_8 BIT(15)
36#define OCR_VDD_MIN_2V7 GENMASK(23, 15)
37#define OCR_VDD_MIN_2V0 GENMASK(14, 8)
38#define OCR_VDD_MIN_1V7 BIT(7)
39
Jun Nie028cb122018-06-28 16:38:00 +080040#define MMC_RSP_48 BIT(0)
41#define MMC_RSP_136 BIT(1) /* 136 bit response */
42#define MMC_RSP_CRC BIT(2) /* expect valid crc */
43#define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */
44#define MMC_RSP_BUSY BIT(4) /* device may be busy */
45
46/* JEDEC 4.51 chapter 6.12 */
47#define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC)
48#define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY)
Yann Gautierf2e8b162018-09-28 16:48:37 +020049#define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC)
Jun Nie028cb122018-06-28 16:38:00 +080050#define MMC_RESPONSE_R3 (MMC_RSP_48)
51#define MMC_RESPONSE_R4 (MMC_RSP_48)
Yann Gautierf2e8b162018-09-28 16:48:37 +020052#define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
53#define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
54#define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
Yann Gautier1e5e85a2018-07-03 18:32:12 +020055
56/* Value randomly chosen for eMMC RCA, it should be > 1 */
57#define MMC_FIX_RCA 6
58#define RCA_SHIFT_OFFSET 16
59
60#define CMD_EXTCSD_PARTITION_CONFIG 179
61#define CMD_EXTCSD_BUS_WIDTH 183
62#define CMD_EXTCSD_HS_TIMING 185
63#define CMD_EXTCSD_SEC_CNT 212
64
65#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
66#define PART_CFG_PARTITION1_ACCESS (U(1) << 0)
67
68/* Values in EXT CSD register */
69#define MMC_BUS_WIDTH_1 U(0)
70#define MMC_BUS_WIDTH_4 U(1)
71#define MMC_BUS_WIDTH_8 U(2)
72#define MMC_BUS_WIDTH_DDR_4 U(5)
73#define MMC_BUS_WIDTH_DDR_8 U(6)
74#define MMC_BOOT_MODE_BACKWARD (U(0) << 3)
75#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3)
76#define MMC_BOOT_MODE_DDR (U(2) << 3)
77
78#define EXTCSD_SET_CMD (U(0) << 24)
79#define EXTCSD_SET_BITS (U(1) << 24)
80#define EXTCSD_CLR_BITS (U(2) << 24)
81#define EXTCSD_WRITE_BYTES (U(3) << 24)
82#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
83#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
84#define EXTCSD_CMD_SET_NORMAL U(1)
85
86#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
87#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
88#define CSD_TRAN_SPEED_MULT_SHIFT 3
89
90#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
91#define STATUS_READY_FOR_DATA BIT(8)
92#define STATUS_SWITCH_ERROR BIT(7)
93#define MMC_GET_STATE(x) (((x) >> 9) & 0xf)
94#define MMC_STATE_IDLE 0
95#define MMC_STATE_READY 1
96#define MMC_STATE_IDENT 2
97#define MMC_STATE_STBY 3
98#define MMC_STATE_TRAN 4
99#define MMC_STATE_DATA 5
100#define MMC_STATE_RCV 6
101#define MMC_STATE_PRG 7
102#define MMC_STATE_DIS 8
103#define MMC_STATE_BTST 9
104#define MMC_STATE_SLP 10
105
106#define MMC_FLAG_CMD23 (U(1) << 0)
107
108#define CMD8_CHECK_PATTERN U(0xAA)
109#define VHS_2_7_3_6_V BIT(8)
110
111#define SD_SCR_BUS_WIDTH_1 BIT(8)
112#define SD_SCR_BUS_WIDTH_4 BIT(10)
113
114struct mmc_cmd {
115 unsigned int cmd_idx;
116 unsigned int cmd_arg;
117 unsigned int resp_type;
118 unsigned int resp_data[4];
119};
120
121struct mmc_ops {
122 void (*init)(void);
123 int (*send_cmd)(struct mmc_cmd *cmd);
124 int (*set_ios)(unsigned int clk, unsigned int width);
125 int (*prepare)(int lba, uintptr_t buf, size_t size);
126 int (*read)(int lba, uintptr_t buf, size_t size);
127 int (*write)(int lba, const uintptr_t buf, size_t size);
128};
129
130struct mmc_csd_emmc {
131 unsigned int not_used: 1;
132 unsigned int crc: 7;
133 unsigned int ecc: 2;
134 unsigned int file_format: 2;
135 unsigned int tmp_write_protect: 1;
136 unsigned int perm_write_protect: 1;
137 unsigned int copy: 1;
138 unsigned int file_format_grp: 1;
139
140 unsigned int reserved_1: 5;
141 unsigned int write_bl_partial: 1;
142 unsigned int write_bl_len: 4;
143 unsigned int r2w_factor: 3;
144 unsigned int default_ecc: 2;
145 unsigned int wp_grp_enable: 1;
146
147 unsigned int wp_grp_size: 5;
148 unsigned int erase_grp_mult: 5;
149 unsigned int erase_grp_size: 5;
150 unsigned int c_size_mult: 3;
151 unsigned int vdd_w_curr_max: 3;
152 unsigned int vdd_w_curr_min: 3;
153 unsigned int vdd_r_curr_max: 3;
154 unsigned int vdd_r_curr_min: 3;
155 unsigned int c_size_low: 2;
156
157 unsigned int c_size_high: 10;
158 unsigned int reserved_2: 2;
159 unsigned int dsr_imp: 1;
160 unsigned int read_blk_misalign: 1;
161 unsigned int write_blk_misalign: 1;
162 unsigned int read_bl_partial: 1;
163 unsigned int read_bl_len: 4;
164 unsigned int ccc: 12;
165
166 unsigned int tran_speed: 8;
167 unsigned int nsac: 8;
168 unsigned int taac: 8;
169 unsigned int reserved_3: 2;
170 unsigned int spec_vers: 4;
171 unsigned int csd_structure: 2;
172};
173
174struct mmc_csd_sd_v2 {
175 unsigned int not_used: 1;
176 unsigned int crc: 7;
177 unsigned int reserved_1: 2;
178 unsigned int file_format: 2;
179 unsigned int tmp_write_protect: 1;
180 unsigned int perm_write_protect: 1;
181 unsigned int copy: 1;
182 unsigned int file_format_grp: 1;
183
184 unsigned int reserved_2: 5;
185 unsigned int write_bl_partial: 1;
186 unsigned int write_bl_len: 4;
187 unsigned int r2w_factor: 3;
188 unsigned int reserved_3: 2;
189 unsigned int wp_grp_enable: 1;
190
191 unsigned int wp_grp_size: 7;
192 unsigned int sector_size: 7;
193 unsigned int erase_block_en: 1;
194 unsigned int reserved_4: 1;
195 unsigned int c_size_low: 16;
196
197 unsigned int c_size_high: 6;
198 unsigned int reserved_5: 6;
199 unsigned int dsr_imp: 1;
200 unsigned int read_blk_misalign: 1;
201 unsigned int write_blk_misalign: 1;
202 unsigned int read_bl_partial: 1;
203 unsigned int read_bl_len: 4;
204 unsigned int ccc: 12;
205
206 unsigned int tran_speed: 8;
207 unsigned int nsac: 8;
208 unsigned int taac: 8;
209 unsigned int reserved_6: 6;
210 unsigned int csd_structure: 2;
211};
212
213enum mmc_device_type {
214 MMC_IS_EMMC,
215 MMC_IS_SD,
216 MMC_IS_SD_HC,
217};
218
219struct mmc_device_info {
220 unsigned long long device_size; /* Size of device in bytes */
221 unsigned int block_size; /* Block size in bytes */
222 unsigned int max_bus_freq; /* Max bus freq in Hz */
Tien Hock, Loh313e9002019-03-07 11:34:20 +0800223 unsigned int ocr_voltage; /* OCR voltage */
Yann Gautier1e5e85a2018-07-03 18:32:12 +0200224 enum mmc_device_type mmc_dev_type; /* Type of MMC */
225};
226
Haojian Zhuangd87f0b72018-08-02 14:49:51 +0800227size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size);
228size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size);
229size_t mmc_erase_blocks(int lba, size_t size);
230size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
231size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
232size_t mmc_rpmb_erase_blocks(int lba, size_t size);
Yann Gautier1e5e85a2018-07-03 18:32:12 +0200233int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
234 unsigned int width, unsigned int flags,
235 struct mmc_device_info *device_info);
236
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000237#endif /* MMC_H */