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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Build Options
2=============
3
4The TF-A build system supports the following build options. Unless mentioned
5otherwise, these options are expected to be specified at the build command
6line and are not to be modified in any component makefiles. Note that the
7build system doesn't track dependency for build options. Therefore, if any of
8the build options are changed from a previous build, a clean build must be
9performed.
10
11.. _build_options_common:
12
13Common build options
14--------------------
15
16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
18 code having a smaller resulting size.
19
20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
22 directory containing the SP source, relative to the ``bl32/``; the directory
23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
24
25- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
26 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
27 ``aarch64``.
28
29- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
30 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
31 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
32 :ref:`Firmware Design`.
33
34- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
35 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
36 *Armv8 Architecture Extensions* in :ref:`Firmware Design`.
37
38- ``BL2``: This is an optional build option which specifies the path to BL2
39 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
40 built.
41
42- ``BL2U``: This is an optional build option which specifies the path to
43 BL2U image. In this case, the BL2U in TF-A will not be built.
44
45- ``BL2_AT_EL3``: This is an optional build option that enables the use of
46 BL2 at EL3 execution level.
47
48- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
49 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
50 the RW sections in RAM, while leaving the RO sections in place. This option
51 enable this use-case. For now, this option is only supported when BL2_AT_EL3
52 is set to '1'.
53
54- ``BL31``: This is an optional build option which specifies the path to
55 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
56 be built.
57
58- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
59 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
60 this file name will be used to save the key.
61
62- ``BL32``: This is an optional build option which specifies the path to
63 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
64 be built.
65
66- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
67 Trusted OS Extra1 image for the ``fip`` target.
68
69- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
70 Trusted OS Extra2 image for the ``fip`` target.
71
72- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
73 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
74 this file name will be used to save the key.
75
76- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
77 ``fip`` target in case TF-A BL2 is used.
78
79- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
80 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
81 this file name will be used to save the key.
82
83- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
84 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
85 If enabled, it is needed to use a compiler that supports the option
86 ``-mbranch-protection``. Selects the branch protection features to use:
87- 0: Default value turns off all types of branch protection
88- 1: Enables all types of branch protection features
89- 2: Return address signing to its standard level
90- 3: Extend the signing to include leaf functions
91
92 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
93 and resulting PAuth/BTI features.
94
95 +-------+--------------+-------+-----+
96 | Value | GCC option | PAuth | BTI |
97 +=======+==============+=======+=====+
98 | 0 | none | N | N |
99 +-------+--------------+-------+-----+
100 | 1 | standard | Y | Y |
101 +-------+--------------+-------+-----+
102 | 2 | pac-ret | Y | N |
103 +-------+--------------+-------+-----+
104 | 3 | pac-ret+leaf | Y | N |
105 +-------+--------------+-------+-----+
106
107 This option defaults to 0 and this is an experimental feature.
108 Note that Pointer Authentication is enabled for Non-secure world
109 irrespective of the value of this option if the CPU supports it.
110
111- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
112 compilation of each build. It must be set to a C string (including quotes
113 where applicable). Defaults to a string that contains the time and date of
114 the compilation.
115
116- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
117 build to be uniquely identified. Defaults to the current git commit id.
118
119- ``CFLAGS``: Extra user options appended on the compiler's command line in
120 addition to the options set by the build system.
121
122- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
123 release several CPUs out of reset. It can take either 0 (several CPUs may be
124 brought up) or 1 (only one CPU will ever be brought up during cold reset).
125 Default is 0. If the platform always brings up a single CPU, there is no
126 need to distinguish between primary and secondary CPUs and the boot path can
127 be optimised. The ``plat_is_my_cpu_primary()`` and
128 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
129 to be implemented in this case.
130
Sandrine Bailleuxd4c1d442020-01-15 10:23:25 +0100131- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
132 Defaults to ``tbbr``.
133
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100134- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
135 register state when an unexpected exception occurs during execution of
136 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
137 this is only enabled for a debug build of the firmware.
138
139- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
140 certificate generation tool to create new keys in case no valid keys are
141 present or specified. Allowed options are '0' or '1'. Default is '1'.
142
143- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
144 the AArch32 system registers to be included when saving and restoring the
145 CPU context. The option must be set to 0 for AArch64-only platforms (that
146 is on hardware that does not implement AArch32, or at least not at EL1 and
147 higher ELs). Default value is 1.
148
149- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
150 registers to be included when saving and restoring the CPU context. Default
151 is 0.
152
153- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
154 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
155 registers to be included when saving and restoring the CPU context as
156 part of world switch. Default value is 0 and this is an experimental feature.
157 Note that Pointer Authentication is enabled for Non-secure world irrespective
158 of the value of this flag if the CPU supports it.
159
160- ``DEBUG``: Chooses between a debug and release build. It can take either 0
161 (release) or 1 (debug) as values. 0 is the default.
162
163- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
164 of the binary image. If set to 1, then only the ELF image is built.
165 0 is the default.
166
167- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
168 Board Boot authentication at runtime. This option is meant to be enabled only
169 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
170 flag has to be enabled. 0 is the default.
171
172- ``E``: Boolean option to make warnings into errors. Default is 1.
173
174- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
175 the normal boot flow. It must specify the entry point address of the EL3
176 payload. Please refer to the "Booting an EL3 payload" section for more
177 details.
178
179- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
180 This is an optional architectural feature available on v8.4 onwards. Some
181 v8.2 implementations also implement an AMU and this option can be used to
182 enable this feature on those systems as well. Default is 0.
183
184- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
185 are compiled out. For debug builds, this option defaults to 1, and calls to
186 ``assert()`` are left in place. For release builds, this option defaults to 0
187 and calls to ``assert()`` function are compiled out. This option can be set
188 independently of ``DEBUG``. It can also be used to hide any auxiliary code
189 that is only required for the assertion and does not fit in the assertion
190 itself.
191
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000192- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100193 dumps or not. It is supported in both AArch64 and AArch32. However, in
194 AArch32 the format of the frame records are not defined in the AAPCS and they
195 are defined by the implementation. This implementation of backtrace only
196 supports the format used by GCC when T32 interworking is disabled. For this
197 reason enabling this option in AArch32 will force the compiler to only
198 generate A32 code. This option is enabled by default only in AArch64 debug
199 builds, but this behaviour can be overridden in each platform's Makefile or
200 in the build command line.
201
Sandrine Bailleux11427302019-12-17 09:38:08 +0100202- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO)
zelalem-aweked5f45272019-11-12 16:20:17 -0600203 support in GCC for TF-A. This option is currently only supported for
204 AArch64. Default is 0.
205
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100206- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
207 feature. MPAM is an optional Armv8.4 extension that enables various memory
208 system components and resources to define partitions; software running at
209 various ELs can assign themselves to desired partition to control their
210 performance aspects.
211
212 When this option is set to ``1``, EL3 allows lower ELs to access their own
213 MPAM registers without trapping into EL3. This option doesn't make use of
214 partitioning in EL3, however. Platform initialisation code should configure
215 and use partitions in EL3 as required. This option defaults to ``0``.
216
217- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
218 support within generic code in TF-A. This option is currently only supported
Masahiro Yamadade634f82020-01-17 13:45:14 +0900219 in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100220
221- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
222 Measurement Framework(PMF). Default is 0.
223
224- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
225 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
226 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
227 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
228 software.
229
230- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
231 instrumentation which injects timestamp collection points into TF-A to
232 allow runtime performance to be measured. Currently, only PSCI is
233 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
234 as well. Default is 0.
235
236- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
237 extensions. This is an optional architectural feature for AArch64.
238 The default is 1 but is automatically disabled when the target architecture
239 is AArch32.
240
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100241- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
242 (SVE) for the Non-secure world only. SVE is an optional architectural feature
243 for AArch64. Note that when SVE is enabled for the Non-secure world, access
244 to SIMD and floating-point functionality from the Secure world is disabled.
245 This is to avoid corruption of the Non-secure world data in the Z-registers
246 which are aliased by the SIMD and FP registers. The build option is not
247 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
248 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
249 1. The default is 1 but is automatically disabled when the target
250 architecture is AArch32.
251
252- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
253 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
254 default value is set to "none". "strong" is the recommended stack protection
255 level if this feature is desired. "none" disables the stack protection. For
256 all values other than "none", the ``plat_get_stack_protector_canary()``
257 platform hook needs to be implemented. The value is passed as the last
258 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
259
260- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
261 deprecated platform APIs, helper functions or drivers within Trusted
262 Firmware as error. It can take the value 1 (flag the use of deprecated
263 APIs as error) or 0. The default is 0.
264
265- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
266 targeted at EL3. When set ``0`` (default), no exceptions are expected or
267 handled at EL3, and a panic will result. This is supported only for AArch64
268 builds.
269
270- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
271 injection from lower ELs, and this build option enables lower ELs to use
272 Error Records accessed via System Registers to inject faults. This is
273 applicable only to AArch64 builds.
274
275 This feature is intended for testing purposes only, and is advisable to keep
276 disabled for production images.
277
278- ``FIP_NAME``: This is an optional build option which specifies the FIP
279 filename for the ``fip`` target. Default is ``fip.bin``.
280
281- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
282 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
283
284- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
285 tool to create certificates as per the Chain of Trust described in
286 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to
287 include the certificates in the FIP and FWU_FIP. Default value is '0'.
288
289 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
290 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
291 the corresponding certificates, and to include those certificates in the
292 FIP and FWU_FIP.
293
294 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
295 images will not include support for Trusted Board Boot. The FIP will still
296 include the corresponding certificates. This FIP can be used to verify the
297 Chain of Trust on the host machine through other mechanisms.
298
299 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
300 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
301 will not include the corresponding certificates, causing a boot failure.
302
303- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
304 inherent support for specific EL3 type interrupts. Setting this build option
305 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
306 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
307 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
308 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
309 the Secure Payload interrupts needs to be synchronously handed over to Secure
310 EL1 for handling. The default value of this option is ``0``, which means the
311 Group 0 interrupts are assumed to be handled by Secure EL1.
312
Imre Kisc83f7202020-02-03 14:48:21 +0100313 .. __: platform-interrupt-controller-API.rst
314 .. __: interrupt-framework-design.rst
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100315
316- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
317 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
318 ``0`` (default), these exceptions will be trapped in the current exception
319 level (or in EL1 if the current exception level is EL0).
320
321- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
322 software operations are required for CPUs to enter and exit coherency.
323 However, newer systems exist where CPUs' entry to and exit from coherency
324 is managed in hardware. Such systems require software to only initiate these
325 operations, and the rest is managed in hardware, minimizing active software
326 management. In such systems, this boolean option enables TF-A to carry out
327 build and run-time optimizations during boot and power management operations.
328 This option defaults to 0 and if it is enabled, then it implies
329 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
330
331 If this flag is disabled while the platform which TF-A is compiled for
332 includes cores that manage coherency in hardware, then a compilation error is
333 generated. This is based on the fact that a system cannot have, at the same
334 time, cores that manage coherency in hardware and cores that don't. In other
335 words, a platform cannot have, at the same time, cores that require
336 ``HW_ASSISTED_COHERENCY=1`` and cores that require
337 ``HW_ASSISTED_COHERENCY=0``.
338
339 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
340 translation library (xlat tables v2) must be used; version 1 of translation
341 library is not supported.
342
343- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
344 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
345 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
346 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
347 images.
348
349- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
350 used for generating the PKCS keys and subsequent signing of the certificate.
351 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
352 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
353 compliant and is retained only for compatibility. The default value of this
354 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
355
Gilad Ben-Yossefa6e53422019-09-15 13:29:29 +0300356- ``KEY_SIZE``: This build flag enables the user to select the key size for
357 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
358 depend on the chosen algorithm and the cryptographic module.
359
360 +-----------+------------------------------------+
361 | KEY_ALG | Possible key sizes |
362 +===========+====================================+
363 | rsa | 1024 , 2048 (default), 3072, 4096* |
364 +-----------+------------------------------------+
365 | ecdsa | unavailable |
366 +-----------+------------------------------------+
367
368 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1.
369 Only 3072 bits size is available with CryptoCell 712 SBROM release 2.
370
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100371- ``HASH_ALG``: This build flag enables the user to select the secure hash
372 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
373 The default value of this flag is ``sha256``.
374
375- ``LDFLAGS``: Extra user options appended to the linkers' command line in
376 addition to the one set by the build system.
377
378- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
379 output compiled into the build. This should be one of the following:
380
381 ::
382
383 0 (LOG_LEVEL_NONE)
384 10 (LOG_LEVEL_ERROR)
385 20 (LOG_LEVEL_NOTICE)
386 30 (LOG_LEVEL_WARNING)
387 40 (LOG_LEVEL_INFO)
388 50 (LOG_LEVEL_VERBOSE)
389
390 All log output up to and including the selected log level is compiled into
391 the build. The default value is 40 in debug builds and 20 in release builds.
392
Alexei Fedorov913cb7e2020-01-23 14:27:38 +0000393- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
394 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set.
395 This option defaults to 0 and is an experimental feature in the stage of
396 development.
397
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100398- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
399 specifies the file that contains the Non-Trusted World private key in PEM
400 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
401
402- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
403 optional. It is only needed if the platform makefile specifies that it
404 is required in order to build the ``fwu_fip`` target.
405
406- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
407 contents upon world switch. It can take either 0 (don't save and restore) or
408 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
409 wants the timer registers to be saved and restored.
410
411- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
412 for the BL image. It can be either 0 (include) or 1 (remove). The default
413 value is 0.
414
415- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
416 the underlying hardware is not a full PL011 UART but a minimally compliant
417 generic UART, which is a subset of the PL011. The driver will not access
418 any register that is not part of the SBSA generic UART specification.
419 Default value is 0 (a full PL011 compliant UART is present).
420
421- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
422 must be subdirectory of any depth under ``plat/``, and must contain a
423 platform makefile named ``platform.mk``. For example, to build TF-A for the
424 Arm Juno board, select PLAT=juno.
425
426- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
427 instead of the normal boot flow. When defined, it must specify the entry
428 point address for the preloaded BL33 image. This option is incompatible with
429 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
430 over ``PRELOADED_BL33_BASE``.
431
432- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
433 vector address can be programmed or is fixed on the platform. It can take
434 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
435 programmable reset address, it is expected that a CPU will start executing
436 code directly at the right address, both on a cold and warm reset. In this
437 case, there is no need to identify the entrypoint on boot and the boot path
438 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
439 does not need to be implemented in this case.
440
441- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
442 possible for the PSCI power-state parameter: original and extended State-ID
443 formats. This flag if set to 1, configures the generic PSCI layer to use the
444 extended format. The default value of this flag is 0, which means by default
445 the original power-state format is used by the PSCI implementation. This flag
446 should be specified by the platform makefile and it governs the return value
447 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
448 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
449 set to 1 as well.
450
451- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
452 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
453 or later CPUs.
454
455 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
456 set to ``1``.
457
458 This option is disabled by default.
459
460- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
461 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
462 entrypoint) or 1 (CPU reset to BL31 entrypoint).
463 The default value is 0.
464
465- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
466 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
467 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
468 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
469
470- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
Max Shvetsov06dba292019-12-06 11:50:12 +0000471 file that contains the ROT private key in PEM format and enforces public key
472 hash generation. If ``SAVE_KEYS=1``, this
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100473 file name will be used to save the key.
474
475- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
476 certificate generation tool to save the keys used to establish the Chain of
477 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
478
479- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
480 If a SCP_BL2 image is present then this option must be passed for the ``fip``
481 target.
482
483- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
484 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
485 this file name will be used to save the key.
486
487- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
488 optional. It is only needed if the platform makefile specifies that it
489 is required in order to build the ``fwu_fip`` target.
490
491- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
492 Delegated Exception Interface to BL31 image. This defaults to ``0``.
493
494 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
495 set to ``1``.
496
497- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
498 isolated on separate memory pages. This is a trade-off between security and
499 memory usage. See "Isolating code and read-only data on separate memory
500 pages" section in :ref:`Firmware Design`. This flag is disabled by default and
501 affects all BL images.
502
Samuel Holland31a14e12018-10-17 21:40:18 -0500503- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
504 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
505 allocated in RAM discontiguous from the loaded firmware image. When set, the
506 platform is expected to provide definitons for ``BL31_NOBITS_BASE`` and
507 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
508 sections are placed in RAM immediately following the loaded firmware image.
509
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100510- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
511 This build option is only valid if ``ARCH=aarch64``. The value should be
512 the path to the directory containing the SPD source, relative to
513 ``services/spd/``; the directory is expected to contain a makefile called
514 ``<spd-value>.mk``.
515
516- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
517 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
518 execution in BL1 just before handing over to BL31. At this point, all
519 firmware images have been loaded in memory, and the MMU and caches are
520 turned off. Refer to the "Debugging options" section for more details.
521
Paul Beesleyfe975b42019-09-16 11:29:03 +0000522- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
523 Partition Manager (SPM) implementation. The default value is ``0``.
524
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100525- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
526 secure interrupts (caught through the FIQ line). Platforms can enable
527 this directive if they need to handle such interruption. When enabled,
528 the FIQ are handled in monitor mode and non secure world is not allowed
529 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
530 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
531
532- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
533 Boot feature. When set to '1', BL1 and BL2 images include support to load
534 and verify the certificates and images in a FIP, and BL1 includes support
535 for the Firmware Update. The default value is '0'. Generation and inclusion
536 of certificates in the FIP and FWU_FIP depends upon the value of the
537 ``GENERATE_COT`` option.
538
539 .. warning::
540 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
541 already exist in disk, they will be overwritten without further notice.
542
543- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
544 specifies the file that contains the Trusted World private key in PEM
545 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
546
547- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
548 synchronous, (see "Initializing a BL32 Image" section in
549 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using
550 synchronous method) or 1 (BL32 is initialized using asynchronous method).
551 Default is 0.
552
553- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
554 routing model which routes non-secure interrupts asynchronously from TSP
555 to EL3 causing immediate preemption of TSP. The EL3 is responsible
556 for saving and restoring the TSP context in this routing model. The
557 default routing model (when the value is 0) is to route non-secure
558 interrupts to TSP allowing it to save its context and hand over
559 synchronously to EL3 via an SMC.
560
561 .. note::
562 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
563 must also be set to ``1``.
564
565- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
566 linker. When the ``LINKER`` build variable points to the armlink linker,
567 this flag is enabled automatically. To enable support for armlink, platforms
568 will have to provide a scatter file for the BL image. Currently, Tegra
569 platforms use the armlink support to compile BL3-1 images.
570
571- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
572 memory region in the BL memory map or not (see "Use of Coherent memory in
573 TF-A" section in :ref:`Firmware Design`). It can take the value 1
574 (Coherent memory region is included) or 0 (Coherent memory region is
575 excluded). Default is 1.
576
Ambroise Vincent9660dc12019-07-12 13:47:03 +0100577- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature
578 exposing a virtual filesystem interface through BL31 as a SiP SMC function.
579 Default is 0.
580
Louis Mayencourtbadcac82019-10-24 15:18:46 +0100581- ``USE_FCONF_BASED_IO``: This flag determines whether to use IO based on the
582 firmware configuration framework. This allows moving the io_policies into a
583 configuration device tree, instead of static structure in the code base.
584
585
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100586- ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
587 This feature creates a library of functions to be placed in ROM and thus
588 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default
589 is 0.
590
591- ``V``: Verbose build. If assigned anything other than 0, the build commands
592 are printed. Default is 0.
593
594- ``VERSION_STRING``: String used in the log output for each TF-A image.
595 Defaults to a string formed by concatenating the version number, build type
596 and build string.
597
598- ``W``: Warning level. Some compiler warning options of interest have been
599 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
600 each level enabling more warning options. Default is 0.
601
602- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
603 the CPU after warm boot. This is applicable for platforms which do not
604 require interconnect programming to enable cache coherency (eg: single
605 cluster platforms). If this option is enabled, then warm boot path
606 enables D-caches immediately after enabling MMU. This option defaults to 0.
607
608Debugging options
609-----------------
610
611To compile a debug version and make the build more verbose use
612
613.. code:: shell
614
615 make PLAT=<platform> DEBUG=1 V=1 all
616
617AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
618example DS-5) might not support this and may need an older version of DWARF
619symbols to be emitted by GCC. This can be achieved by using the
620``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
621version to 2 is recommended for DS-5 versions older than 5.16.
622
623When debugging logic problems it might also be useful to disable all compiler
624optimizations by using ``-O0``.
625
626.. warning::
627 Using ``-O0`` could cause output images to be larger and base addresses
628 might need to be recalculated (see the **Memory layout on Arm development
629 platforms** section in the :ref:`Firmware Design`).
630
631Extra debug options can be passed to the build system by setting ``CFLAGS`` or
632``LDFLAGS``:
633
634.. code:: shell
635
636 CFLAGS='-O0 -gdwarf-2' \
637 make PLAT=<platform> DEBUG=1 V=1 all
638
639Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
640ignored as the linker is called directly.
641
642It is also possible to introduce an infinite loop to help in debugging the
643post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
644``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common`
645section. In this case, the developer may take control of the target using a
646debugger when indicated by the console output. When using DS-5, the following
647commands can be used:
648
649::
650
651 # Stop target execution
652 interrupt
653
654 #
655 # Prepare your debugging environment, e.g. set breakpoints
656 #
657
658 # Jump over the debug loop
659 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
660
661 # Resume execution
662 continue
663
664--------------
665
Imre Kisc83f7202020-02-03 14:48:21 +0100666*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*