Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <string.h> |
| 32 | #include <assert.h> |
| 33 | #include <arch_helpers.h> |
| 34 | #include <platform.h> |
| 35 | #include <bl31.h> |
| 36 | #include <bl_common.h> |
| 37 | #include <pl011.h> |
| 38 | #include <bakery_lock.h> |
| 39 | #include <cci400.h> |
| 40 | #include <gic.h> |
| 41 | #include <fvp_pwrc.h> |
| 42 | |
| 43 | /******************************************************************************* |
| 44 | * Declarations of linker defined symbols which will help us find the layout |
| 45 | * of trusted SRAM |
| 46 | ******************************************************************************/ |
| 47 | #if defined (__GNUC__) |
| 48 | extern unsigned long __BL31_RO_BASE__; |
| 49 | extern unsigned long __BL31_STACKS_BASE__; |
| 50 | extern unsigned long __BL31_COHERENT_RAM_BASE__; |
| 51 | extern unsigned long __BL31_RW_BASE__; |
| 52 | |
| 53 | #define BL31_RO_BASE __BL31_RO_BASE__ |
| 54 | #define BL31_STACKS_BASE __BL31_STACKS_BASE__ |
| 55 | #define BL31_COHERENT_RAM_BASE __BL31_COHERENT_RAM_BASE__ |
| 56 | #define BL31_RW_BASE __BL31_RW_BASE__ |
| 57 | |
| 58 | #else |
| 59 | #error "Unknown compiler." |
| 60 | #endif |
| 61 | |
| 62 | /******************************************************************************* |
| 63 | * This data structures holds information copied by BL31 from BL2 to pass |
| 64 | * control to the non-trusted software images. A per-cpu entry was created to |
| 65 | * use the same structure in the warm boot path but that's not the case right |
| 66 | * now. Persisting with this approach for the time being. TODO: Can this be |
| 67 | * moved out of device memory. |
| 68 | ******************************************************************************/ |
| 69 | el_change_info ns_entry_info[PLATFORM_CORE_COUNT] |
| 70 | __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), |
| 71 | section("tzfw_coherent_mem"))) = {0}; |
| 72 | |
| 73 | /* Data structure which holds the extents of the trusted SRAM for BL31 */ |
| 74 | static meminfo bl31_tzram_layout |
| 75 | __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), |
| 76 | section("tzfw_coherent_mem"))) = {0}; |
| 77 | |
| 78 | meminfo bl31_get_sec_mem_layout(void) |
| 79 | { |
| 80 | return bl31_tzram_layout; |
| 81 | } |
| 82 | |
| 83 | /******************************************************************************* |
| 84 | * Return information about passing control to the non-trusted software images |
| 85 | * to common code.TODO: In the initial architecture, the image after BL31 will |
| 86 | * always run in the non-secure state. In the final architecture there |
| 87 | * will be a series of images. This function will need enhancement then |
| 88 | ******************************************************************************/ |
| 89 | el_change_info *bl31_get_next_image_info(unsigned long mpidr) |
| 90 | { |
| 91 | return &ns_entry_info[platform_get_core_pos(mpidr)]; |
| 92 | } |
| 93 | |
| 94 | /******************************************************************************* |
| 95 | * Perform any BL31 specific platform actions. Here we copy parameters passed |
| 96 | * by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they are lost |
| 97 | * (potentially). This is done before the MMU is initialized so that the memory |
| 98 | * layout can be used while creating page tables. |
| 99 | ******************************************************************************/ |
| 100 | void bl31_early_platform_setup(meminfo *mem_layout, |
| 101 | void *data, |
| 102 | unsigned long mpidr) |
| 103 | { |
| 104 | el_change_info *image_info = (el_change_info *) data; |
| 105 | unsigned int lin_index = platform_get_core_pos(mpidr); |
| 106 | |
| 107 | /* Setup the BL31 memory layout */ |
| 108 | bl31_tzram_layout.total_base = mem_layout->total_base; |
| 109 | bl31_tzram_layout.total_size = mem_layout->total_size; |
| 110 | bl31_tzram_layout.free_base = mem_layout->free_base; |
| 111 | bl31_tzram_layout.free_size = mem_layout->free_size; |
| 112 | bl31_tzram_layout.attr = mem_layout->attr; |
| 113 | bl31_tzram_layout.next = 0; |
| 114 | |
| 115 | /* Save information about jumping into the NS world */ |
| 116 | ns_entry_info[lin_index].entrypoint = image_info->entrypoint; |
| 117 | ns_entry_info[lin_index].spsr = image_info->spsr; |
| 118 | ns_entry_info[lin_index].args = image_info->args; |
| 119 | ns_entry_info[lin_index].security_state = image_info->security_state; |
| 120 | ns_entry_info[lin_index].next = image_info->next; |
| 121 | |
| 122 | /* Initialize the platform config for future decision making */ |
| 123 | platform_config_setup(); |
| 124 | } |
| 125 | |
| 126 | /******************************************************************************* |
| 127 | * Initialize the gic, configure the CLCD and zero out variables needed by the |
| 128 | * secondaries to boot up correctly. |
| 129 | ******************************************************************************/ |
| 130 | void bl31_platform_setup() |
| 131 | { |
| 132 | unsigned int reg_val; |
| 133 | |
| 134 | /* Initialize the gic cpu and distributor interfaces */ |
| 135 | gic_setup(); |
| 136 | |
| 137 | /* |
| 138 | * TODO: Configure the CLCD before handing control to |
| 139 | * linux. Need to see if a separate driver is needed |
| 140 | * instead. |
| 141 | */ |
| 142 | mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0); |
| 143 | mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| 144 | (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16)); |
| 145 | |
| 146 | /* Allow access to the System counter timer module */ |
| 147 | reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); |
| 148 | reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); |
| 149 | reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); |
| 150 | mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val); |
| 151 | mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); |
| 152 | |
| 153 | reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1)); |
| 154 | mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); |
| 155 | |
| 156 | /* Intialize the power controller */ |
| 157 | fvp_pwrc_setup(); |
| 158 | |
| 159 | /* Topologies are best known to the platform. */ |
| 160 | plat_setup_topology(); |
| 161 | } |
| 162 | |
| 163 | /******************************************************************************* |
| 164 | * Perform the very early platform specific architectural setup here. At the |
| 165 | * moment this is only intializes the mmu in a quick and dirty way. |
| 166 | ******************************************************************************/ |
| 167 | void bl31_plat_arch_setup() |
| 168 | { |
| 169 | unsigned long sctlr; |
| 170 | |
| 171 | /* Enable instruction cache. */ |
| 172 | sctlr = read_sctlr(); |
| 173 | sctlr |= SCTLR_I_BIT; |
| 174 | write_sctlr(sctlr); |
| 175 | |
| 176 | write_vbar((unsigned long) runtime_exceptions); |
| 177 | configure_mmu(&bl31_tzram_layout, |
| 178 | (unsigned long) &BL31_RO_BASE, |
| 179 | (unsigned long) &BL31_STACKS_BASE, |
| 180 | (unsigned long) &BL31_COHERENT_RAM_BASE, |
| 181 | (unsigned long) &BL31_RW_BASE); |
| 182 | } |
| 183 | |
| 184 | /******************************************************************************* |
| 185 | * TODO: Move GIC setup to a separate file in case it is needed by other BL |
| 186 | * stages or ELs |
| 187 | * TODO: Revisit if priorities are being set such that no non-secure interrupt |
| 188 | * can have a higher priority than a secure one as recommended in the GICv2 spec |
| 189 | *******************************************************************************/ |
| 190 | |
| 191 | /******************************************************************************* |
| 192 | * This function does some minimal GICv3 configuration. The Firmware itself does |
| 193 | * not fully support GICv3 at this time and relies on GICv2 emulation as |
| 194 | * provided by GICv3. This function allows software (like Linux) in later stages |
| 195 | * to use full GICv3 features. |
| 196 | *******************************************************************************/ |
| 197 | void gicv3_cpuif_setup(void) |
| 198 | { |
| 199 | unsigned int scr_val, val, base; |
| 200 | |
| 201 | /* |
| 202 | * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep |
| 203 | * bit set. In order to allow interrupts to get routed to the CPU we |
| 204 | * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep |
| 205 | * to clear (GICv3 Architecture specification 5.4.23). |
| 206 | * GICR_WAKER is NOT banked per CPU, compute the correct base address |
| 207 | * per CPU. |
| 208 | * |
| 209 | * TODO: |
| 210 | * For GICv4 we also need to adjust the Base address based on |
| 211 | * GICR_TYPER.VLPIS |
| 212 | */ |
| 213 | base = BASE_GICR_BASE + |
| 214 | (platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT); |
| 215 | val = gicr_read_waker(base); |
| 216 | |
| 217 | val &= ~WAKER_PS; |
| 218 | gicr_write_waker(base, val); |
| 219 | dsb(); |
| 220 | |
| 221 | /* We need to wait for ChildrenAsleep to clear. */ |
| 222 | val = gicr_read_waker(base); |
| 223 | while (val & WAKER_CA) { |
| 224 | val = gicr_read_waker(base); |
| 225 | } |
| 226 | |
| 227 | /* |
| 228 | * We need to set SCR_EL3.NS in order to see GICv3 non-secure state. |
| 229 | * Restore SCR_EL3.NS again before exit. |
| 230 | */ |
| 231 | scr_val = read_scr(); |
| 232 | write_scr(scr_val | SCR_NS_BIT); |
| 233 | |
| 234 | /* |
| 235 | * By default EL2 and NS-EL1 software should be able to enable GICv3 |
| 236 | * System register access without any configuration at EL3. But it turns |
| 237 | * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So |
| 238 | * we need to set it here again. In order to do that we need to enable |
| 239 | * register access. We leave it enabled as it should be fine and might |
| 240 | * prevent problems with later software trying to access GIC System |
| 241 | * Registers. |
| 242 | */ |
| 243 | val = read_icc_sre_el3(); |
| 244 | write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE); |
| 245 | |
| 246 | val = read_icc_sre_el2(); |
| 247 | write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE); |
| 248 | |
| 249 | write_icc_pmr_el1(MAX_PRI_VAL); |
| 250 | |
| 251 | /* Restore SCR_EL3 */ |
| 252 | write_scr(scr_val); |
| 253 | } |
| 254 | |
| 255 | /******************************************************************************* |
| 256 | * This function does some minimal GICv3 configuration when cores go |
| 257 | * down. |
| 258 | *******************************************************************************/ |
| 259 | void gicv3_cpuif_deactivate(void) |
| 260 | { |
| 261 | unsigned int val, base; |
| 262 | |
| 263 | /* |
| 264 | * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and |
| 265 | * wait for GICR_WAKER.ChildrenAsleep to get set. |
| 266 | * (GICv3 Architecture specification 5.4.23). |
| 267 | * GICR_WAKER is NOT banked per CPU, compute the correct base address |
| 268 | * per CPU. |
| 269 | * |
| 270 | * TODO: |
| 271 | * For GICv4 we also need to adjust the Base address based on |
| 272 | * GICR_TYPER.VLPIS |
| 273 | */ |
| 274 | base = BASE_GICR_BASE + |
| 275 | (platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT); |
| 276 | val = gicr_read_waker(base); |
| 277 | val |= WAKER_PS; |
| 278 | gicr_write_waker(base, val); |
| 279 | dsb(); |
| 280 | |
| 281 | /* We need to wait for ChildrenAsleep to set. */ |
| 282 | val = gicr_read_waker(base); |
| 283 | while ((val & WAKER_CA) == 0) { |
| 284 | val = gicr_read_waker(base); |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | |
| 289 | /******************************************************************************* |
| 290 | * Enable secure interrupts and use FIQs to route them. Disable legacy bypass |
| 291 | * and set the priority mask register to allow all interrupts to trickle in. |
| 292 | ******************************************************************************/ |
| 293 | void gic_cpuif_setup(unsigned int gicc_base) |
| 294 | { |
| 295 | unsigned int val; |
| 296 | |
| 297 | val = gicc_read_iidr(gicc_base); |
| 298 | |
| 299 | /* |
| 300 | * If GICv3 we need to do a bit of additional setup. We want to |
| 301 | * allow default GICv2 behaviour but allow the next stage to |
| 302 | * enable full gicv3 features. |
| 303 | */ |
| 304 | if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) { |
| 305 | gicv3_cpuif_setup(); |
| 306 | } |
| 307 | |
| 308 | val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0; |
| 309 | val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; |
| 310 | |
| 311 | gicc_write_pmr(gicc_base, MAX_PRI_VAL); |
| 312 | gicc_write_ctlr(gicc_base, val); |
| 313 | } |
| 314 | |
| 315 | /******************************************************************************* |
| 316 | * Place the cpu interface in a state where it can never make a cpu exit wfi as |
| 317 | * as result of an asserted interrupt. This is critical for powering down a cpu |
| 318 | ******************************************************************************/ |
| 319 | void gic_cpuif_deactivate(unsigned int gicc_base) |
| 320 | { |
| 321 | unsigned int val; |
| 322 | |
| 323 | /* Disable secure, non-secure interrupts and disable their bypass */ |
| 324 | val = gicc_read_ctlr(gicc_base); |
| 325 | val &= ~(ENABLE_GRP0 | ENABLE_GRP1); |
| 326 | val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; |
| 327 | val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; |
| 328 | gicc_write_ctlr(gicc_base, val); |
| 329 | |
| 330 | val = gicc_read_iidr(gicc_base); |
| 331 | |
| 332 | /* |
| 333 | * If GICv3 we need to do a bit of additional setup. Make sure the |
| 334 | * RDIST is put to sleep. |
| 335 | */ |
| 336 | if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) { |
| 337 | gicv3_cpuif_deactivate(); |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | /******************************************************************************* |
| 342 | * Per cpu gic distributor setup which will be done by all cpus after a cold |
| 343 | * boot/hotplug. This marks out the secure interrupts & enables them. |
| 344 | ******************************************************************************/ |
| 345 | void gic_pcpu_distif_setup(unsigned int gicd_base) |
| 346 | { |
| 347 | gicd_write_igroupr(gicd_base, 0, ~0); |
| 348 | |
| 349 | gicd_clr_igroupr(gicd_base, IRQ_SEC_PHY_TIMER); |
| 350 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_0); |
| 351 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_1); |
| 352 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_2); |
| 353 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_3); |
| 354 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_4); |
| 355 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_5); |
| 356 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_6); |
| 357 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_7); |
| 358 | |
| 359 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_PHY_TIMER, MAX_PRI_VAL); |
| 360 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_0, MAX_PRI_VAL); |
| 361 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_1, MAX_PRI_VAL); |
| 362 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_2, MAX_PRI_VAL); |
| 363 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_3, MAX_PRI_VAL); |
| 364 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_4, MAX_PRI_VAL); |
| 365 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_5, MAX_PRI_VAL); |
| 366 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_6, MAX_PRI_VAL); |
| 367 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_7, MAX_PRI_VAL); |
| 368 | |
| 369 | gicd_set_isenabler(gicd_base, IRQ_SEC_PHY_TIMER); |
| 370 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_0); |
| 371 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_1); |
| 372 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_2); |
| 373 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_3); |
| 374 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_4); |
| 375 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_5); |
| 376 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_6); |
| 377 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_7); |
| 378 | } |
| 379 | |
| 380 | /******************************************************************************* |
| 381 | * Global gic distributor setup which will be done by the primary cpu after a |
| 382 | * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It |
| 383 | * then enables the secure GIC distributor interface. |
| 384 | ******************************************************************************/ |
| 385 | void gic_distif_setup(unsigned int gicd_base) |
| 386 | { |
| 387 | unsigned int ctr, num_ints, ctlr; |
| 388 | |
| 389 | /* Disable the distributor before going further */ |
| 390 | ctlr = gicd_read_ctlr(gicd_base); |
| 391 | ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1); |
| 392 | gicd_write_ctlr(gicd_base, ctlr); |
| 393 | |
| 394 | /* |
| 395 | * Mark out non-secure interrupts. Calculate number of |
| 396 | * IGROUPR registers to consider. Will be equal to the |
| 397 | * number of IT_LINES |
| 398 | */ |
| 399 | num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; |
| 400 | num_ints++; |
| 401 | for (ctr = 0; ctr < num_ints; ctr++) |
| 402 | gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0); |
| 403 | |
| 404 | /* Configure secure interrupts now */ |
| 405 | gicd_clr_igroupr(gicd_base, IRQ_TZ_WDOG); |
| 406 | gicd_set_ipriorityr(gicd_base, IRQ_TZ_WDOG, MAX_PRI_VAL); |
| 407 | gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG, |
| 408 | platform_get_core_pos(read_mpidr())); |
| 409 | gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG); |
| 410 | gic_pcpu_distif_setup(gicd_base); |
| 411 | |
| 412 | gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0); |
| 413 | } |
| 414 | |
| 415 | void gic_setup(void) |
| 416 | { |
| 417 | unsigned int gicd_base, gicc_base; |
| 418 | |
| 419 | gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR); |
| 420 | gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); |
| 421 | |
| 422 | gic_cpuif_setup(gicc_base); |
| 423 | gic_distif_setup(gicd_base); |
| 424 | } |