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git01.mediatek.com / filogic / atf / 309ac01a3aa2721515aea18920be22404b11bb46 / . / plat / intel / soc / agilex / include / platform_def.h
blob: 277862a30738580a592caf75c166ad027a50f144 [file] [log] [blame]
Hadi Asyrafi616da772019-06-27 11:34:03 +0800[diff] [blame]1/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2019, Intel Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef PLATFORM_DEF_H
9#define PLATFORM_DEF_H
10
11#include <arch.h>
12#include <common/interrupt_props.h>
13#include <common/tbbr/tbbr_img_def.h>
14#include <plat/common/common_def.h>
15
16
17#define PLAT_CPUID_RELEASE 0xffe1b000
Hadi Asyrafi309ac012019-08-01 14:48:39 +0800[diff] [blame^]18#define PLAT_SEC_ENTRY 0xffe1b008
Hadi Asyrafi616da772019-06-27 11:34:03 +0800[diff] [blame]19
20/* Define next boot image name and offset */
21#define PLAT_NS_IMAGE_OFFSET 0x50000
22#define PLAT_HANDOFF_OFFSET 0xFFE3F000
23
24/*******************************************************************************
25 * Platform binary types for linking
26 ******************************************************************************/
27#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
28#define PLATFORM_LINKER_ARCH aarch64
29
30/* Agilex supports up to 124GB RAM */
31#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
32#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
33
34
35/*******************************************************************************
36 * Generic platform constants
37 ******************************************************************************/
38#define PLAT_PRIMARY_CPU 0
39#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0
40
41/* Size of cacheable stacks */
42#define PLATFORM_STACK_SIZE 0x2000
43
44/* PSCI related constant */
45#define PLAT_NUM_POWER_DOMAINS 5
46#define PLAT_MAX_PWR_LVL 1
47#define PLAT_MAX_RET_STATE 1
48#define PLAT_MAX_OFF_STATE 2
49#define PLATFORM_SYSTEM_COUNT 1
50#define PLATFORM_CLUSTER_COUNT 1
51#define PLATFORM_CLUSTER0_CORE_COUNT 4
52#define PLATFORM_CLUSTER1_CORE_COUNT 0
53#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
54 PLATFORM_CLUSTER0_CORE_COUNT)
55#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
56
57/* Interrupt related constant */
58
59#define INTEL_AGX_IRQ_SEC_PHY_TIMER 29
60
61#define INTEL_AGX_IRQ_SEC_SGI_0 8
62#define INTEL_AGX_IRQ_SEC_SGI_1 9
63#define INTEL_AGX_IRQ_SEC_SGI_2 10
64#define INTEL_AGX_IRQ_SEC_SGI_3 11
65#define INTEL_AGX_IRQ_SEC_SGI_4 12
66#define INTEL_AGX_IRQ_SEC_SGI_5 13
67#define INTEL_AGX_IRQ_SEC_SGI_6 14
68#define INTEL_AGX_IRQ_SEC_SGI_7 15
69
70#define TSP_IRQ_SEC_PHY_TIMER INTEL_AGX_IRQ_SEC_PHY_TIMER
71#define TSP_SEC_MEM_BASE BL32_BASE
72#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
73/*******************************************************************************
74 * Platform memory map related constants
75 ******************************************************************************/
76#define DRAM_BASE (0x0)
77#define DRAM_SIZE (0x80000000)
78
79#define OCRAM_BASE (0xFFE00000)
80#define OCRAM_SIZE (0x00040000)
81
82#define MEM64_BASE (0x0100000000)
83#define MEM64_SIZE (0x1F00000000)
84
85#define DEVICE1_BASE (0x80000000)
86#define DEVICE1_SIZE (0x60000000)
87
88#define DEVICE2_BASE (0xF7000000)
89#define DEVICE2_SIZE (0x08E00000)
90
91#define DEVICE3_BASE (0xFFFC0000)
92#define DEVICE3_SIZE (0x00008000)
93
94#define DEVICE4_BASE (0x2000000000)
95#define DEVICE4_SIZE (0x0100000000)
96
97/*******************************************************************************
98 * BL31 specific defines.
99 ******************************************************************************/
100/*
101 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
102 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
103 * little space for growth.
104 */
105
106
107#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
108
109#define BL1_RO_BASE (0xffe00000)
110#define BL1_RO_LIMIT (0xffe0f000)
111#define BL1_RW_BASE (0xffe10000)
112#define BL1_RW_LIMIT (0xffe1ffff)
113#define BL1_RW_SIZE (0x14000)
114
115#define BL2_BASE (0xffe00000)
116#define BL2_LIMIT (0xffe1b000)
117
118#define BL31_BASE (0xffe1c000)
119#define BL31_LIMIT (0xffe3bfff)
120
121/*******************************************************************************
122 * Platform specific page table and MMU setup constants
123 ******************************************************************************/
124#define MAX_XLAT_TABLES 8
125#define MAX_MMAP_REGIONS 16
126
127/*******************************************************************************
128 * Declarations and constants to access the mailboxes safely. Each mailbox is
129 * aligned on the biggest cache line size in the platform. This is known only
130 * to the platform as it might have a combination of integrated and external
131 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
132 * line at any cache level. They could belong to different cpus/clusters &
133 * get written while being protected by different locks causing corruption of
134 * a valid mailbox address.
135 ******************************************************************************/
136#define CACHE_WRITEBACK_SHIFT 6
137#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
138
139#define PLAT_GIC_BASE (0xFFFC0000)
140#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
141#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
142#define PLAT_GICR_BASE 0
143
144/*******************************************************************************
145 * UART related constants
146 ******************************************************************************/
147#define PLAT_UART0_BASE (0xFFC02000)
148#define PLAT_UART1_BASE (0xFFC02100)
149
150#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
151
152#define PLAT_BAUDRATE (115200)
153#define PLAT_UART_CLOCK (100000000)
154
155/*******************************************************************************
156 * System counter frequency related constants
157 ******************************************************************************/
158#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
159#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
160
161#define PLAT_INTEL_AGX_GICD_BASE PLAT_GICD_BASE
162#define PLAT_INTEL_AGX_GICC_BASE PLAT_GICC_BASE
163
164/*
165 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
166 * terminology. On a GICv2 system or mode, the lists will be merged and treated
167 * as Group 0 interrupts.
168 */
169#define PLAT_INTEL_AGX_G1S_IRQ_PROPS(grp) \
170 INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
171 grp, GIC_INTR_CFG_LEVEL), \
172 INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
173 GIC_INTR_CFG_EDGE), \
174 INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
175 GIC_INTR_CFG_EDGE), \
176 INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
177 GIC_INTR_CFG_EDGE), \
178 INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
179 GIC_INTR_CFG_EDGE), \
180 INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
181 GIC_INTR_CFG_EDGE), \
182 INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
183 GIC_INTR_CFG_EDGE), \
184 INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
185 GIC_INTR_CFG_EDGE), \
186 INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
187 GIC_INTR_CFG_EDGE)
188
189#define PLAT_INTEL_AGX_G0_IRQ_PROPS(grp)
190
191#define MAX_IO_HANDLES 4
192#define MAX_IO_DEVICES 4
193#define MAX_IO_BLOCK_DEVICES 2
194
195#endif /* PLATFORM_DEF_H */
196