Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #include <asm_macros.S> |
| 9 | #include <cortex_a72.h> |
| 10 | #include <marvell_def.h> |
| 11 | #include <platform_def.h> |
| 12 | #ifndef PLAT_a3700 |
| 13 | #include <ccu.h> |
| 14 | #include <cache_llc.h> |
| 15 | #endif |
| 16 | |
| 17 | .weak plat_marvell_calc_core_pos |
| 18 | .weak plat_my_core_pos |
| 19 | .globl plat_crash_console_init |
| 20 | .globl plat_crash_console_putc |
| 21 | .globl platform_mem_init |
| 22 | .globl disable_mmu_dcache |
| 23 | .globl invalidate_tlb_all |
| 24 | .globl platform_unmap_sram |
| 25 | .globl disable_sram |
| 26 | .globl disable_icache |
| 27 | .globl invalidate_icache_all |
| 28 | .globl marvell_exit_bootrom |
| 29 | .globl ca72_l2_enable_unique_clean |
| 30 | |
| 31 | /* ----------------------------------------------------- |
| 32 | * unsigned int plat_my_core_pos(void) |
| 33 | * This function uses the plat_marvell_calc_core_pos() |
| 34 | * definition to get the index of the calling CPU. |
| 35 | * ----------------------------------------------------- |
| 36 | */ |
| 37 | func plat_my_core_pos |
| 38 | mrs x0, mpidr_el1 |
| 39 | b plat_marvell_calc_core_pos |
| 40 | endfunc plat_my_core_pos |
| 41 | |
| 42 | /* ----------------------------------------------------- |
| 43 | * unsigned int plat_marvell_calc_core_pos(uint64_t mpidr) |
| 44 | * Helper function to calculate the core position. |
| 45 | * With this function: CorePos = (ClusterId * 2) + |
| 46 | * CoreId |
| 47 | * ----------------------------------------------------- |
| 48 | */ |
| 49 | func plat_marvell_calc_core_pos |
| 50 | and x1, x0, #MPIDR_CPU_MASK |
| 51 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 52 | add x0, x1, x0, LSR #7 |
| 53 | ret |
| 54 | endfunc plat_marvell_calc_core_pos |
| 55 | |
| 56 | /* --------------------------------------------- |
| 57 | * int plat_crash_console_init(void) |
| 58 | * Function to initialize the crash console |
| 59 | * without a C Runtime to print crash report. |
| 60 | * Clobber list : x0, x1, x2 |
| 61 | * --------------------------------------------- |
| 62 | */ |
| 63 | func plat_crash_console_init |
| 64 | mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE |
| 65 | mov_imm x1, PLAT_MARVELL_CRASH_UART_CLK_IN_HZ |
| 66 | mov_imm x2, MARVELL_CONSOLE_BAUDRATE |
| 67 | b console_core_init |
| 68 | endfunc plat_crash_console_init |
| 69 | |
| 70 | /* --------------------------------------------- |
| 71 | * int plat_crash_console_putc(int c) |
| 72 | * Function to print a character on the crash |
| 73 | * console without a C Runtime. |
| 74 | * Clobber list : x1, x2 |
| 75 | * --------------------------------------------- |
| 76 | */ |
| 77 | func plat_crash_console_putc |
| 78 | mov_imm x1, PLAT_MARVELL_CRASH_UART_BASE |
| 79 | b console_core_putc |
| 80 | endfunc plat_crash_console_putc |
| 81 | |
| 82 | /* --------------------------------------------------------------------- |
| 83 | * We don't need to carry out any memory initialization on ARM |
| 84 | * platforms. The Secure RAM is accessible straight away. |
| 85 | * --------------------------------------------------------------------- |
| 86 | */ |
| 87 | func platform_mem_init |
| 88 | ret |
| 89 | endfunc platform_mem_init |
| 90 | |
| 91 | /* ----------------------------------------------------- |
| 92 | * Disable icache, dcache, and MMU |
| 93 | * ----------------------------------------------------- |
| 94 | */ |
| 95 | func disable_mmu_dcache |
| 96 | mrs x0, sctlr_el3 |
| 97 | bic x0, x0, 0x1 /* M bit - MMU */ |
| 98 | bic x0, x0, 0x4 /* C bit - Dcache L1 & L2 */ |
| 99 | msr sctlr_el3, x0 |
| 100 | isb |
| 101 | b mmu_off |
| 102 | mmu_off: |
| 103 | ret |
| 104 | endfunc disable_mmu_dcache |
| 105 | |
| 106 | /* ----------------------------------------------------- |
| 107 | * Disable all TLB entries |
| 108 | * ----------------------------------------------------- |
| 109 | */ |
| 110 | func invalidate_tlb_all |
| 111 | tlbi alle3 |
| 112 | dsb sy |
| 113 | isb |
| 114 | ret |
| 115 | endfunc invalidate_tlb_all |
| 116 | |
| 117 | /* ----------------------------------------------------- |
| 118 | * Disable the i cache |
| 119 | * ----------------------------------------------------- |
| 120 | */ |
| 121 | func disable_icache |
| 122 | mrs x0, sctlr_el3 |
| 123 | bic x0, x0, 0x1000 /* I bit - Icache L1 & L2 */ |
| 124 | msr sctlr_el3, x0 |
| 125 | isb |
| 126 | ret |
| 127 | endfunc disable_icache |
| 128 | |
| 129 | /* ----------------------------------------------------- |
| 130 | * Disable all of the i caches |
| 131 | * ----------------------------------------------------- |
| 132 | */ |
| 133 | func invalidate_icache_all |
| 134 | ic ialluis |
| 135 | isb sy |
| 136 | ret |
| 137 | endfunc invalidate_icache_all |
| 138 | |
| 139 | /* ----------------------------------------------------- |
| 140 | * Clear the SRAM enabling bit to unmap SRAM |
| 141 | * ----------------------------------------------------- |
| 142 | */ |
| 143 | func platform_unmap_sram |
| 144 | ldr x0, =CCU_SRAM_WIN_CR |
| 145 | str wzr, [x0] |
| 146 | ret |
| 147 | endfunc platform_unmap_sram |
| 148 | |
| 149 | /* ----------------------------------------------------- |
| 150 | * Disable the SRAM |
| 151 | * ----------------------------------------------------- |
| 152 | */ |
| 153 | func disable_sram |
| 154 | /* Disable the line lockings. They must be disabled expictly |
| 155 | * or the OS will have problems using the cache */ |
| 156 | ldr x1, =MASTER_LLC_TC0_LOCK |
| 157 | str wzr, [x1] |
| 158 | |
| 159 | /* Invalidate all ways */ |
| 160 | ldr w1, =LLC_WAY_MASK |
| 161 | ldr x0, =MASTER_L2X0_INV_WAY |
| 162 | str w1, [x0] |
| 163 | |
| 164 | /* Finally disable LLC */ |
| 165 | ldr x0, =MASTER_LLC_CTRL |
| 166 | str wzr, [x0] |
| 167 | |
| 168 | ret |
| 169 | endfunc disable_sram |
| 170 | |
| 171 | /* ----------------------------------------------------- |
| 172 | * Operation when exit bootROM: |
| 173 | * Disable the MMU |
| 174 | * Disable and invalidate the dcache |
| 175 | * Unmap and disable the SRAM |
| 176 | * Disable and invalidate the icache |
| 177 | * ----------------------------------------------------- |
| 178 | */ |
| 179 | func marvell_exit_bootrom |
| 180 | /* Save the system restore address */ |
| 181 | mov x28, x0 |
| 182 | |
| 183 | /* Close the caches and MMU */ |
| 184 | bl disable_mmu_dcache |
| 185 | |
| 186 | /* |
| 187 | * There is nothing important in the caches now, |
| 188 | * so invalidate them instead of cleaning. |
| 189 | */ |
| 190 | adr x0, __RW_START__ |
| 191 | adr x1, __RW_END__ |
| 192 | sub x1, x1, x0 |
| 193 | bl inv_dcache_range |
| 194 | bl invalidate_tlb_all |
| 195 | |
| 196 | /* |
| 197 | * Clean the memory mapping of SRAM |
| 198 | * the DDR mapping will remain to enable boot image to execute |
| 199 | */ |
| 200 | bl platform_unmap_sram |
| 201 | |
| 202 | /* Disable the SRAM */ |
| 203 | bl disable_sram |
| 204 | |
| 205 | /* Disable and invalidate icache */ |
| 206 | bl disable_icache |
| 207 | bl invalidate_icache_all |
| 208 | |
| 209 | mov x0, x28 |
| 210 | br x0 |
| 211 | endfunc marvell_exit_bootrom |
| 212 | |
| 213 | /* |
| 214 | * Enable L2 UniqueClean evictions with data |
| 215 | */ |
| 216 | func ca72_l2_enable_unique_clean |
| 217 | |
| 218 | mrs x0, CORTEX_A72_L2ACTLR_EL1 |
| 219 | orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN |
| 220 | msr CORTEX_A72_L2ACTLR_EL1, x0 |
| 221 | |
| 222 | ret |
| 223 | endfunc ca72_l2_enable_unique_clean |