Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __TZC_COMMON_H__ |
| 8 | #define __TZC_COMMON_H__ |
| 9 | |
| 10 | /* |
| 11 | * Offset of core registers from the start of the base of configuration |
| 12 | * registers for each region. |
| 13 | */ |
| 14 | |
| 15 | /* ID Registers */ |
| 16 | #define PID0_OFF 0xfe0 |
| 17 | #define PID1_OFF 0xfe4 |
| 18 | #define PID2_OFF 0xfe8 |
| 19 | #define PID3_OFF 0xfec |
| 20 | #define PID4_OFF 0xfd0 |
| 21 | #define CID0_OFF 0xff0 |
| 22 | #define CID1_OFF 0xff4 |
| 23 | #define CID2_OFF 0xff8 |
| 24 | #define CID3_OFF 0xffc |
| 25 | |
| 26 | /* Bit positions of TZC_ACTION registers */ |
| 27 | #define TZC_ACTION_RV_SHIFT 0 |
| 28 | #define TZC_ACTION_RV_MASK 0x3 |
| 29 | #define TZC_ACTION_RV_LOWOK 0x0 |
| 30 | #define TZC_ACTION_RV_LOWERR 0x1 |
| 31 | #define TZC_ACTION_RV_HIGHOK 0x2 |
| 32 | #define TZC_ACTION_RV_HIGHERR 0x3 |
| 33 | |
| 34 | /* Used along with 'tzc_region_attributes_t' below */ |
| 35 | #define TZC_REGION_ATTR_S_RD_SHIFT 30 |
| 36 | #define TZC_REGION_ATTR_S_WR_SHIFT 31 |
| 37 | #define TZC_REGION_ATTR_F_EN_SHIFT 0 |
| 38 | #define TZC_REGION_ATTR_SEC_SHIFT 30 |
| 39 | #define TZC_REGION_ATTR_S_RD_MASK 0x1 |
| 40 | #define TZC_REGION_ATTR_S_WR_MASK 0x1 |
| 41 | #define TZC_REGION_ATTR_SEC_MASK 0x3 |
| 42 | |
| 43 | #define TZC_REGION_ACCESS_WR_EN_SHIFT 16 |
| 44 | #define TZC_REGION_ACCESS_RD_EN_SHIFT 0 |
| 45 | #define TZC_REGION_ACCESS_ID_MASK 0xf |
| 46 | |
| 47 | /* Macros for allowing Non-Secure access to a region based on NSAID */ |
| 48 | #define TZC_REGION_ACCESS_RD(nsaid) \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame^] | 49 | ((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 50 | TZC_REGION_ACCESS_RD_EN_SHIFT) |
| 51 | #define TZC_REGION_ACCESS_WR(nsaid) \ |
Sathees Balya | 30952cc | 2018-09-27 14:41:02 +0100 | [diff] [blame^] | 52 | ((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \ |
Vikram Kanigiri | 1eabdbc | 2016-01-28 17:22:16 +0000 | [diff] [blame] | 53 | TZC_REGION_ACCESS_WR_EN_SHIFT) |
| 54 | #define TZC_REGION_ACCESS_RDWR(nsaid) \ |
| 55 | (TZC_REGION_ACCESS_RD(nsaid) | \ |
| 56 | TZC_REGION_ACCESS_WR(nsaid)) |
| 57 | |
| 58 | #ifndef __ASSEMBLY__ |
| 59 | |
| 60 | /* Returns offset of registers to program for a given region no */ |
| 61 | #define TZC_REGION_OFFSET(region_size, region_no) \ |
| 62 | ((region_size) * (region_no)) |
| 63 | |
| 64 | /* |
| 65 | * What type of action is expected when an access violation occurs. |
| 66 | * The memory requested is returned as zero. But we can also raise an event to |
| 67 | * let the system know it happened. |
| 68 | * We can raise an interrupt(INT) and/or cause an exception(ERR). |
| 69 | * TZC_ACTION_NONE - No interrupt, no Exception |
| 70 | * TZC_ACTION_ERR - No interrupt, raise exception -> sync external |
| 71 | * data abort |
| 72 | * TZC_ACTION_INT - Raise interrupt, no exception |
| 73 | * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync |
| 74 | * external data abort |
| 75 | */ |
| 76 | typedef enum { |
| 77 | TZC_ACTION_NONE = 0, |
| 78 | TZC_ACTION_ERR = 1, |
| 79 | TZC_ACTION_INT = 2, |
| 80 | TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) |
| 81 | } tzc_action_t; |
| 82 | |
| 83 | /* |
| 84 | * Controls secure access to a region. If not enabled secure access is not |
| 85 | * allowed to region. |
| 86 | */ |
| 87 | typedef enum { |
| 88 | TZC_REGION_S_NONE = 0, |
| 89 | TZC_REGION_S_RD = 1, |
| 90 | TZC_REGION_S_WR = 2, |
| 91 | TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) |
| 92 | } tzc_region_attributes_t; |
| 93 | |
| 94 | #endif /* __ASSEMBLY__ */ |
| 95 | #endif /* __TZC_COMMON_H__ */ |