blob: 31f778790e09151876a5407181bdcde3366d3b19 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Douglas Raillard21362a92016-12-02 13:51:54 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000031#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <bl_common.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35
36 .globl bl2_entrypoint
37
38
Achin Gupta4f6ad662013-10-25 09:08:21 +010039
Andrew Thoelke38bde412014-03-18 13:46:55 +000040func bl2_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +010041 /*---------------------------------------------
Yatharth Kochar57d334c2015-10-29 12:47:02 +000042 * Save from x1 the extents of the tzram
43 * available to BL2 for future use.
44 * x0 is not currently used.
Achin Gupta4f6ad662013-10-25 09:08:21 +010045 * ---------------------------------------------
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +000046 */
47 mov x20, x1
Achin Gupta4f6ad662013-10-25 09:08:21 +010048
49 /* ---------------------------------------------
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000050 * Set the exception vector to something sane.
51 * ---------------------------------------------
52 */
53 adr x0, early_exceptions
54 msr vbar_el1, x0
Achin Guptaed1744e2014-08-04 23:13:10 +010055 isb
56
57 /* ---------------------------------------------
58 * Enable the SError interrupt now that the
59 * exception vectors have been setup.
60 * ---------------------------------------------
61 */
62 msr daifclr, #DAIF_ABT_BIT
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000063
64 /* ---------------------------------------------
Achin Gupta9f098352014-07-18 18:38:28 +010065 * Enable the instruction cache, stack pointer
66 * and data access alignment checks
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000067 * ---------------------------------------------
68 */
Achin Gupta9f098352014-07-18 18:38:28 +010069 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000070 mrs x0, sctlr_el1
Achin Gupta9f098352014-07-18 18:38:28 +010071 orr x0, x0, x1
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000072 msr sctlr_el1, x0
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000073 isb
74
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000075 /* ---------------------------------------------
Achin Guptae9c4a642015-09-11 16:03:13 +010076 * Invalidate the RW memory used by the BL2
77 * image. This includes the data and NOBITS
78 * sections. This is done to safeguard against
79 * possible corruption of this memory by dirty
80 * cache lines in a system cache as a result of
81 * use by an earlier boot loader stage.
82 * ---------------------------------------------
83 */
84 adr x0, __RW_START__
85 adr x1, __RW_END__
86 sub x1, x1, x0
87 bl inv_dcache_range
88
89 /* ---------------------------------------------
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000090 * Zero out NOBITS sections. There are 2 of them:
91 * - the .bss section;
92 * - the coherent memory section.
93 * ---------------------------------------------
94 */
95 ldr x0, =__BSS_START__
96 ldr x1, =__BSS_SIZE__
Douglas Raillard21362a92016-12-02 13:51:54 +000097 bl zeromem
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000098
Soby Mathew2ae20432015-01-08 18:02:44 +000099#if USE_COHERENT_MEM
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000100 ldr x0, =__COHERENT_RAM_START__
101 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
Douglas Raillard21362a92016-12-02 13:51:54 +0000102 bl zeromem
Soby Mathew2ae20432015-01-08 18:02:44 +0000103#endif
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000104
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105 /* --------------------------------------------
Achin Guptaf4a97092014-06-25 19:26:22 +0100106 * Allocate a stack whose memory will be marked
107 * as Normal-IS-WBWA when the MMU is enabled.
108 * There is no risk of reading stale stack
109 * memory after enabling the MMU as only the
110 * primary cpu is running at the moment.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111 * --------------------------------------------
112 */
Soby Mathew3700a922015-07-13 11:21:11 +0100113 bl plat_set_my_stack
Achin Gupta4f6ad662013-10-25 09:08:21 +0100114
115 /* ---------------------------------------------
116 * Perform early platform setup & platform
117 * specific early arch. setup e.g. mmu setup
118 * ---------------------------------------------
119 */
Yatharth Kochar57d334c2015-10-29 12:47:02 +0000120 mov x0, x20
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121 bl bl2_early_platform_setup
122 bl bl2_plat_arch_setup
123
124 /* ---------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100125 * Jump to main function.
126 * ---------------------------------------------
127 */
128 bl bl2_main
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000129
130 /* ---------------------------------------------
131 * Should never reach this point.
132 * ---------------------------------------------
133 */
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000134 no_ret plat_panic_handler
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000135
Kévin Petita877c252015-03-24 14:03:57 +0000136endfunc bl2_entrypoint