blob: b7db1f0d1a826958df59e0e7c25e4b3323c19824 [file] [log] [blame]
Harry Liebeleaec5902013-12-12 13:00:29 +00001/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <stdint.h>
32#include <arch.h>
33#include <platform.h>
34#include <gic.h>
35#include <gic_v3.h>
36#include <debug.h>
37
38uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr)
39{
40 uint32_t cpu_aff, gicr_aff;
41 uint64_t gicr_typer;
42 uintptr_t addr;
43
44 /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level
45 * mask is the same.
46 */
47 cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) <<
48 GICV3_AFF0_SHIFT;
49 cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) <<
50 GICV3_AFF1_SHIFT;
51 cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) <<
52 GICV3_AFF2_SHIFT;
53 cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) <<
54 GICV3_AFF3_SHIFT;
55
56 addr = gicr_base;
57 do {
58 gicr_typer = gicr_read_typer(addr);
59
60 gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) &
61 GICR_TYPER_AFF_MASK;
62 if (cpu_aff == gicr_aff) {
Harry Liebeld19e4972014-02-24 12:01:27 +000063 /* Disable this print for now as it appears every time
64 * when using PSCI CPU_SUSPEND.
65 * TODO: Print this only the first time for each CPU.
66 * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n",
67 * mpidr, addr);
68 */
Harry Liebeleaec5902013-12-12 13:00:29 +000069 return addr;
70 }
71
72 /* TODO:
73 * For GICv4 we need to adjust the Base address based on
74 * GICR_TYPER.VLPIS
75 */
76 addr += (1 << GICR_PCPUBASE_SHIFT);
77
78 } while (!(gicr_typer & GICR_TYPER_LAST));
79
80 /* If we get here we did not find a match. */
81 ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr);
82 return (uintptr_t)NULL;
83}