Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 1 | /* |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 8 | * Driver for GIC-600 specific features. This driver only overrides |
| 9 | * APIs that are different to those generic ones in GICv3 driver. |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 10 | * |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 11 | * GIC-600 supports independently power-gating redistributor interface. |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 12 | */ |
| 13 | |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 14 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | |
| 16 | #include <arch_helpers.h> |
| 17 | #include <drivers/arm/gicv3.h> |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 18 | |
| 19 | #include "gicv3_private.h" |
| 20 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 21 | /* GIC-600 specific register offsets */ |
Douglas Raillard | 1bd2d74 | 2017-08-03 15:59:49 +0100 | [diff] [blame] | 22 | #define GICR_PWRR 0x24 |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 23 | |
| 24 | /* GICR_PWRR fields */ |
| 25 | #define PWRR_RDPD_SHIFT 0 |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 26 | #define PWRR_RDAG_SHIFT 1 |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 27 | #define PWRR_RDGPD_SHIFT 2 |
| 28 | #define PWRR_RDGPO_SHIFT 3 |
| 29 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 30 | #define PWRR_RDPD (1 << PWRR_RDPD_SHIFT) |
| 31 | #define PWRR_RDAG (1 << PWRR_RDAG_SHIFT) |
Douglas Raillard | 1bd2d74 | 2017-08-03 15:59:49 +0100 | [diff] [blame] | 32 | #define PWRR_RDGPD (1 << PWRR_RDGPD_SHIFT) |
| 33 | #define PWRR_RDGPO (1 << PWRR_RDGPO_SHIFT) |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 34 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 35 | /* |
| 36 | * Values to write to GICR_PWRR register to power redistributor |
| 37 | * for operating through the core (GICR_PWRR.RDAG = 0) |
| 38 | */ |
Douglas Raillard | 1bd2d74 | 2017-08-03 15:59:49 +0100 | [diff] [blame] | 39 | #define PWRR_ON (0 << PWRR_RDPD_SHIFT) |
| 40 | #define PWRR_OFF (1 << PWRR_RDPD_SHIFT) |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 41 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 42 | /* GIC-600 specific accessor functions */ |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 43 | static void gicr_write_pwrr(uintptr_t base, unsigned int val) |
| 44 | { |
Douglas Raillard | 1bd2d74 | 2017-08-03 15:59:49 +0100 | [diff] [blame] | 45 | mmio_write_32(base + GICR_PWRR, val); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 46 | } |
| 47 | |
| 48 | static uint32_t gicr_read_pwrr(uintptr_t base) |
| 49 | { |
Douglas Raillard | 1bd2d74 | 2017-08-03 15:59:49 +0100 | [diff] [blame] | 50 | return mmio_read_32(base + GICR_PWRR); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 51 | } |
| 52 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 53 | static void gicr_wait_group_not_in_transit(uintptr_t base) |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 54 | { |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 55 | /* Check group not transitioning: RDGPD == RDGPO */ |
| 56 | while (((gicr_read_pwrr(base) & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) != |
| 57 | ((gicr_read_pwrr(base) & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT)) |
| 58 | ; |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | static void gic600_pwr_on(uintptr_t base) |
| 62 | { |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 63 | do { /* Wait until group not transitioning */ |
| 64 | gicr_wait_group_not_in_transit(base); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 65 | |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 66 | /* Power on redistributor */ |
| 67 | gicr_write_pwrr(base, PWRR_ON); |
| 68 | |
| 69 | /* |
| 70 | * Wait until the power on state is reflected. |
| 71 | * If RDPD == 0 then powered on. |
| 72 | */ |
| 73 | } while ((gicr_read_pwrr(base) & PWRR_RDPD) != PWRR_ON); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | static void gic600_pwr_off(uintptr_t base) |
| 77 | { |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 78 | /* Wait until group not transitioning */ |
| 79 | gicr_wait_group_not_in_transit(base); |
| 80 | |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 81 | /* Power off redistributor */ |
| 82 | gicr_write_pwrr(base, PWRR_OFF); |
| 83 | |
| 84 | /* |
| 85 | * If this is the last man, turning this redistributor frame off will |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 86 | * result in the group itself being powered off and RDGPD = 1. |
| 87 | * In that case, wait as long as it's in transition, or has aborted |
| 88 | * the transition altogether for any reason. |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 89 | */ |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 90 | if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0) { |
| 91 | /* Wait until group not transitioning */ |
| 92 | gicr_wait_group_not_in_transit(base); |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 93 | } |
| 94 | } |
| 95 | |
Soby Mathew | 327548c | 2017-07-13 15:19:51 +0100 | [diff] [blame] | 96 | void gicv3_distif_pre_save(unsigned int proc_num) |
| 97 | { |
| 98 | arm_gicv3_distif_pre_save(proc_num); |
| 99 | } |
| 100 | |
| 101 | void gicv3_distif_post_restore(unsigned int proc_num) |
| 102 | { |
| 103 | arm_gicv3_distif_post_restore(proc_num); |
| 104 | } |
| 105 | |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 106 | /* |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 107 | * Power off GIC-600 redistributor |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 108 | */ |
| 109 | void gicv3_rdistif_off(unsigned int proc_num) |
| 110 | { |
| 111 | uintptr_t gicr_base; |
| 112 | |
| 113 | assert(gicv3_driver_data); |
| 114 | assert(proc_num < gicv3_driver_data->rdistif_num); |
| 115 | assert(gicv3_driver_data->rdistif_base_addrs); |
| 116 | |
| 117 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
| 118 | assert(gicr_base); |
| 119 | |
| 120 | /* Attempt to power redistributor off */ |
| 121 | gic600_pwr_off(gicr_base); |
| 122 | } |
| 123 | |
| 124 | /* |
Alexei Fedorov | 88fba67 | 2019-07-31 13:24:22 +0100 | [diff] [blame] | 125 | * Power on GIC-600 redistributor |
Jeenu Viswambharan | d7a901e | 2016-12-06 16:15:22 +0000 | [diff] [blame] | 126 | */ |
| 127 | void gicv3_rdistif_on(unsigned int proc_num) |
| 128 | { |
| 129 | uintptr_t gicr_base; |
| 130 | |
| 131 | assert(gicv3_driver_data); |
| 132 | assert(proc_num < gicv3_driver_data->rdistif_num); |
| 133 | assert(gicv3_driver_data->rdistif_base_addrs); |
| 134 | |
| 135 | gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; |
| 136 | assert(gicr_base); |
| 137 | |
| 138 | /* Power redistributor on */ |
| 139 | gic600_pwr_on(gicr_base); |
| 140 | } |