| Yatharth Kochar | 5d36121 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Yatharth Kochar | 5d36121 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <bl1.h> |
| 10 | #include <bl_common.h> |
| 11 | |
| 12 | .globl bl1_aarch32_smc_handler |
| 13 | |
| 14 | |
| 15 | func bl1_aarch32_smc_handler |
| 16 | /* ------------------------------------------------ |
| 17 | * SMC in BL1 is handled assuming that the MMU is |
| 18 | * turned off by BL2. |
| 19 | * ------------------------------------------------ |
| 20 | */ |
| 21 | |
| 22 | /* ---------------------------------------------- |
| 23 | * Only RUN_IMAGE SMC is supported. |
| 24 | * ---------------------------------------------- |
| 25 | */ |
| 26 | mov r8, #BL1_SMC_RUN_IMAGE |
| 27 | cmp r8, r0 |
| 28 | blne report_exception |
| 29 | |
| 30 | /* ------------------------------------------------ |
| 31 | * Make sure only Secure world reaches here. |
| 32 | * ------------------------------------------------ |
| 33 | */ |
| 34 | ldcopr r8, SCR |
| 35 | tst r8, #SCR_NS_BIT |
| 36 | blne report_exception |
| 37 | |
| 38 | /* --------------------------------------------------------------------- |
| 39 | * Pass control to next secure image. |
| 40 | * Here it expects r1 to contain the address of a entry_point_info_t |
| 41 | * structure describing the BL entrypoint. |
| 42 | * --------------------------------------------------------------------- |
| 43 | */ |
| 44 | mov r8, r1 |
| 45 | mov r0, r1 |
| 46 | bl bl1_print_next_bl_ep_info |
| 47 | |
| 48 | #if SPIN_ON_BL1_EXIT |
| 49 | bl print_debug_loop_message |
| 50 | debug_loop: |
| 51 | b debug_loop |
| 52 | #endif |
| 53 | |
| 54 | mov r0, r8 |
| 55 | bl bl1_plat_prepare_exit |
| 56 | |
| 57 | stcopr r0, TLBIALL |
| 58 | dsb sy |
| 59 | isb |
| 60 | |
| 61 | /* |
| 62 | * Extract PC and SPSR based on struct `entry_point_info_t` |
| 63 | * and load it in LR and SPSR registers respectively. |
| 64 | */ |
| 65 | ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] |
| 66 | ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] |
| 67 | msr spsr, r1 |
| 68 | |
| 69 | add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET |
| 70 | ldm r8, {r0, r1, r2, r3} |
| 71 | eret |
| 72 | endfunc bl1_aarch32_smc_handler |