| Konstantin Porotchkin | f69ec58 | 2018-06-07 18:31:14 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2018 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #include <mmio.h> |
| 9 | #include <mss_mem.h> |
| 10 | #include <platform.h> |
| 11 | #include <plat_pm_trace.h> |
| 12 | |
| 13 | #ifdef PM_TRACE_ENABLE |
| 14 | |
| 15 | /* core trace APIs */ |
| 16 | core_trace_func funcTbl[PLATFORM_CORE_COUNT] = { |
| 17 | pm_core_0_trace, |
| 18 | pm_core_1_trace, |
| 19 | pm_core_2_trace, |
| 20 | pm_core_3_trace}; |
| 21 | |
| 22 | /***************************************************************************** |
| 23 | * pm_core0_trace |
| 24 | * pm_core1_trace |
| 25 | * pm_core2_trace |
| 26 | * pm_core_3trace |
| 27 | * |
| 28 | * This functions set trace info into core cyclic trace queue in MSS SRAM |
| 29 | * memory space |
| 30 | ***************************************************************************** |
| 31 | */ |
| 32 | void pm_core_0_trace(unsigned int trace) |
| 33 | { |
| 34 | unsigned int current_position_core_0 = |
| 35 | mmio_read_32(AP_MSS_ATF_CORE_0_CTRL_BASE); |
| 36 | mmio_write_32((AP_MSS_ATF_CORE_0_INFO_BASE + |
| 37 | (current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)), |
| 38 | mmio_read_32(AP_MSS_TIMER_BASE)); |
| 39 | mmio_write_32((AP_MSS_ATF_CORE_0_INFO_TRACE + |
| 40 | (current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)), |
| 41 | trace); |
| 42 | mmio_write_32(AP_MSS_ATF_CORE_0_CTRL_BASE, |
| 43 | ((current_position_core_0 + 1) & |
| 44 | AP_MSS_ATF_TRACE_SIZE_MASK)); |
| 45 | } |
| 46 | |
| 47 | void pm_core_1_trace(unsigned int trace) |
| 48 | { |
| 49 | unsigned int current_position_core_1 = |
| 50 | mmio_read_32(AP_MSS_ATF_CORE_1_CTRL_BASE); |
| 51 | mmio_write_32((AP_MSS_ATF_CORE_1_INFO_BASE + |
| 52 | (current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)), |
| 53 | mmio_read_32(AP_MSS_TIMER_BASE)); |
| 54 | mmio_write_32((AP_MSS_ATF_CORE_1_INFO_TRACE + |
| 55 | (current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)), |
| 56 | trace); |
| 57 | mmio_write_32(AP_MSS_ATF_CORE_1_CTRL_BASE, |
| 58 | ((current_position_core_1 + 1) & |
| 59 | AP_MSS_ATF_TRACE_SIZE_MASK)); |
| 60 | } |
| 61 | |
| 62 | void pm_core_2_trace(unsigned int trace) |
| 63 | { |
| 64 | unsigned int current_position_core_2 = |
| 65 | mmio_read_32(AP_MSS_ATF_CORE_2_CTRL_BASE); |
| 66 | mmio_write_32((AP_MSS_ATF_CORE_2_INFO_BASE + |
| 67 | (current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)), |
| 68 | mmio_read_32(AP_MSS_TIMER_BASE)); |
| 69 | mmio_write_32((AP_MSS_ATF_CORE_2_INFO_TRACE + |
| 70 | (current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)), |
| 71 | trace); |
| 72 | mmio_write_32(AP_MSS_ATF_CORE_2_CTRL_BASE, |
| 73 | ((current_position_core_2 + 1) & |
| 74 | AP_MSS_ATF_TRACE_SIZE_MASK)); |
| 75 | } |
| 76 | |
| 77 | void pm_core_3_trace(unsigned int trace) |
| 78 | { |
| 79 | unsigned int current_position_core_3 = |
| 80 | mmio_read_32(AP_MSS_ATF_CORE_3_CTRL_BASE); |
| 81 | mmio_write_32((AP_MSS_ATF_CORE_3_INFO_BASE + |
| 82 | (current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)), |
| 83 | mmio_read_32(AP_MSS_TIMER_BASE)); |
| 84 | mmio_write_32((AP_MSS_ATF_CORE_3_INFO_TRACE + |
| 85 | (current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)), |
| 86 | trace); |
| 87 | mmio_write_32(AP_MSS_ATF_CORE_3_CTRL_BASE, |
| 88 | ((current_position_core_3 + 1) & |
| 89 | AP_MSS_ATF_TRACE_SIZE_MASK)); |
| 90 | } |
| 91 | #endif /* PM_TRACE_ENABLE */ |