Joel Goddard | a1c50ab | 2022-09-21 21:52:28 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021-2022, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <neoverse_v2.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
| 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
| 17 | #error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 18 | #endif |
| 19 | |
| 20 | /* 64-bit only core */ |
| 21 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 22 | #error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 23 | #endif |
| 24 | |
| 25 | #if WORKAROUND_CVE_2022_23960 |
| 26 | wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2 |
| 27 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 28 | |
| 29 | /* ---------------------------------------------------- |
| 30 | * HW will do the cache maintenance while powering down |
| 31 | * ---------------------------------------------------- |
| 32 | */ |
| 33 | func neoverse_v2_core_pwr_dwn |
| 34 | /* --------------------------------------------------- |
| 35 | * Enable CPU power down bit in power control register |
| 36 | * --------------------------------------------------- |
| 37 | */ |
| 38 | mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1 |
| 39 | orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 40 | msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0 |
Moritz Fischer | 9887006 | 2023-07-06 00:01:23 +0000 | [diff] [blame] | 41 | #if ERRATA_V2_2801372 |
| 42 | mov x15, x30 |
| 43 | bl cpu_get_rev_var |
| 44 | bl errata_neoverse_v2_2801372_wa |
| 45 | mov x30, x15 |
| 46 | #endif /* ERRATA_V2_2801372 */ |
Joel Goddard | a1c50ab | 2022-09-21 21:52:28 +0530 | [diff] [blame] | 47 | isb |
| 48 | ret |
| 49 | endfunc neoverse_v2_core_pwr_dwn |
| 50 | |
| 51 | func check_errata_cve_2022_23960 |
| 52 | #if WORKAROUND_CVE_2022_23960 |
| 53 | mov x0, #ERRATA_APPLIES |
| 54 | #else |
| 55 | mov x0, #ERRATA_MISSING |
| 56 | #endif |
| 57 | ret |
| 58 | endfunc check_errata_cve_2022_23960 |
| 59 | |
Moritz Fischer | 9887006 | 2023-07-06 00:01:23 +0000 | [diff] [blame] | 60 | /* ---------------------------------------------------- |
| 61 | * Errata Workaround for Neoverse V2 Errata #2801372 |
| 62 | * This applies to revisions <= r0p1 and is fixed in r0p2. |
| 63 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 64 | * Shall clobber: x0-x17 |
| 65 | * ---------------------------------------------------- |
| 66 | */ |
| 67 | func errata_neoverse_v2_2801372_wa |
| 68 | mov x17, x30 |
| 69 | bl check_errata_2801372 |
| 70 | cbz x0, 1f |
| 71 | |
| 72 | /* dsb before isb of power down sequence */ |
| 73 | dsb sy |
| 74 | 1: |
| 75 | ret x17 |
| 76 | endfunc errata_neoverse_v2_2801372_wa |
| 77 | |
| 78 | func check_errata_2801372 |
| 79 | /* Applies to all revisions <= r0p1 */ |
| 80 | mov x1, #0x01 |
| 81 | b cpu_rev_var_ls |
| 82 | endfunc check_errata_2801372 |
| 83 | |
Joel Goddard | a1c50ab | 2022-09-21 21:52:28 +0530 | [diff] [blame] | 84 | func neoverse_v2_reset_func |
| 85 | /* Disable speculative loads */ |
| 86 | msr SSBS, xzr |
| 87 | |
| 88 | #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 |
| 89 | /* |
| 90 | * The Neoverse V2 vectors are overridden to apply |
| 91 | * errata mitigation on exception entry from lower ELs. |
| 92 | */ |
| 93 | adr x0, wa_cve_vbar_neoverse_v2 |
| 94 | msr vbar_el3, x0 |
| 95 | #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ |
| 96 | isb |
| 97 | ret |
| 98 | endfunc neoverse_v2_reset_func |
| 99 | |
| 100 | #if REPORT_ERRATA |
| 101 | /* |
| 102 | * Errata printing function for Neoverse V2. Must follow AAPCS. |
| 103 | */ |
| 104 | func neoverse_v2_errata_report |
| 105 | stp x8, x30, [sp, #-16]! |
| 106 | |
| 107 | bl cpu_get_rev_var |
| 108 | mov x8, x0 |
| 109 | |
| 110 | /* |
| 111 | * Report all errata. The revision-variant information is passed to |
| 112 | * checking functions of each errata. |
| 113 | */ |
| 114 | report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960 |
Moritz Fischer | 9887006 | 2023-07-06 00:01:23 +0000 | [diff] [blame] | 115 | report_errata ERRATA_V2_2801372, neoverse_v2, 2801372 |
Joel Goddard | a1c50ab | 2022-09-21 21:52:28 +0530 | [diff] [blame] | 116 | |
| 117 | ldp x8, x30, [sp], #16 |
| 118 | ret |
| 119 | endfunc neoverse_v2_errata_report |
| 120 | #endif |
| 121 | |
| 122 | /* --------------------------------------------- |
| 123 | * This function provides Neoverse V2- |
| 124 | * specific register information for crash |
| 125 | * reporting. It needs to return with x6 |
| 126 | * pointing to a list of register names in ascii |
| 127 | * and x8 - x15 having values of registers to be |
| 128 | * reported. |
| 129 | * --------------------------------------------- |
| 130 | */ |
| 131 | .section .rodata.neoverse_v2_regs, "aS" |
| 132 | neoverse_v2_regs: /* The ascii list of register names to be reported */ |
| 133 | .asciz "cpuectlr_el1", "" |
| 134 | |
| 135 | func neoverse_v2_cpu_reg_dump |
| 136 | adr x6, neoverse_v2_regs |
| 137 | mrs x8, NEOVERSE_V2_CPUECTLR_EL1 |
| 138 | ret |
| 139 | endfunc neoverse_v2_cpu_reg_dump |
| 140 | |
| 141 | declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \ |
| 142 | neoverse_v2_reset_func, \ |
| 143 | neoverse_v2_core_pwr_dwn |