| Pankaj Gupta | 90ae1a0 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLAT_DEF_H |
| 9 | #define PLAT_DEF_H |
| 10 | |
| 11 | #include <arch.h> |
| 12 | #include <cortex_a72.h> |
| 13 | /* Required without TBBR. |
| 14 | * To include the defines for DDR PHY |
| 15 | * Images. |
| 16 | */ |
| 17 | #include <tbbr_img_def.h> |
| 18 | |
| 19 | #include <policy.h> |
| 20 | #include <soc.h> |
| 21 | |
| 22 | #if defined(IMAGE_BL31) |
| 23 | #define LS_SYS_TIMCTL_BASE 0x2890000 |
| 24 | #define PLAT_LS_NSTIMER_FRAME_ID 0 |
| 25 | #define LS_CONFIG_CNTACR 1 |
| 26 | #endif |
| 27 | |
| 28 | #define NXP_SYSCLK_FREQ 100000000 |
| 29 | #define NXP_DDRCLK_FREQ 100000000 |
| 30 | |
| 31 | /* UART related definition */ |
| 32 | #define NXP_CONSOLE_ADDR NXP_UART_ADDR |
| 33 | #define NXP_CONSOLE_BAUDRATE 115200 |
| 34 | |
| 35 | /* Size of cacheable stacks */ |
| 36 | #if defined(IMAGE_BL2) |
| 37 | #if defined(TRUSTED_BOARD_BOOT) |
| 38 | #define PLATFORM_STACK_SIZE 0x2000 |
| 39 | #else |
| 40 | #define PLATFORM_STACK_SIZE 0x1000 |
| 41 | #endif |
| 42 | #elif defined(IMAGE_BL31) |
| 43 | #define PLATFORM_STACK_SIZE 0x1000 |
| 44 | #endif |
| 45 | |
| 46 | /* SD block buffer */ |
| 47 | #define NXP_SD_BLOCK_BUF_SIZE (0x8000) |
| 48 | #define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ |
| 49 | - NXP_SD_BLOCK_BUF_SIZE) |
| 50 | |
| 51 | #ifdef SD_BOOT |
| 52 | #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \ |
| 53 | - NXP_SD_BLOCK_BUF_SIZE) |
| 54 | #else |
| 55 | #define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE) |
| 56 | #endif |
| 57 | |
| 58 | /* IO defines as needed by IO driver framework */ |
| 59 | #define MAX_IO_DEVICES 4 |
| 60 | #define MAX_IO_BLOCK_DEVICES 1 |
| 61 | #define MAX_IO_HANDLES 4 |
| 62 | |
| 63 | #define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ) |
| 64 | |
| 65 | /* |
| 66 | * FIP image defines - Offset at which FIP Image would be present |
| 67 | * Image would include Bl31 , Bl33 and Bl32 (optional) |
| 68 | */ |
| 69 | #ifdef POLICY_FUSE_PROVISION |
| 70 | #define MAX_FIP_DEVICES 3 |
| 71 | #endif |
| 72 | |
| 73 | #ifndef MAX_FIP_DEVICES |
| 74 | #define MAX_FIP_DEVICES 2 |
| 75 | #endif |
| 76 | |
| 77 | /* |
| 78 | * ID of the secure physical generic timer interrupt used by the BL32. |
| 79 | */ |
| 80 | #define BL32_IRQ_SEC_PHY_TIMER 29 |
| 81 | |
| 82 | #define BL31_WDOG_SEC 89 |
| 83 | |
| 84 | #define BL31_NS_WDOG_WS1 108 |
| 85 | |
| 86 | /* |
| 87 | * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 88 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 89 | * as Group 0 interrupts. |
| 90 | */ |
| 91 | #define PLAT_LS_G1S_IRQ_PROPS(grp) \ |
| 92 | INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 93 | GIC_INTR_CFG_EDGE) |
| 94 | |
| 95 | /* SGI 15 and Secure watchdog interrupts assigned to Group 0 */ |
| 96 | #define NXP_IRQ_SEC_SGI_7 15 |
| 97 | |
| 98 | #define PLAT_LS_G0_IRQ_PROPS(grp) \ |
| 99 | INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 100 | GIC_INTR_CFG_EDGE), \ |
| 101 | INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 102 | GIC_INTR_CFG_EDGE), \ |
| 103 | INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ |
| 104 | GIC_INTR_CFG_LEVEL) |
| 105 | #endif |