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git01.mediatek.com / filogic / atf / 2ea0584e81d9a64583f0da98ea752a613a332248 / . / plat / arm / board / tc / fdts / tc_fw_config.dts
blob: b210e75c538912fa3d0122006b6dfb6dc5841dcb [file] [log] [blame]
Usama Arifbec5afd2020-04-17 16:13:39 +0100[diff] [blame]1/*
Boyan Karatotevbf9ba732023-09-28 13:31:51 +0000[diff] [blame]2 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Manish Pandeyf4110242020-06-08 14:48:09 +0100[diff] [blame]7#include <common/tbbr/tbbr_img_def.h>
Boyan Karatotevbf9ba732023-09-28 13:31:51 +0000[diff] [blame]8#include <platform_def.h>
Usama Arifbec5afd2020-04-17 16:13:39 +0100[diff] [blame]9
10/dts-v1/;
11
12/ {
13 dtb-registry {
14 compatible = "fconf,dyn_cfg-dtb_registry";
15
Usama Arifbec5afd2020-04-17 16:13:39 +0100[diff] [blame]16 tb_fw-config {
Manish V Badarkhe64616a52020-05-31 08:53:40 +0100[diff] [blame]17 load-address = <0x0 0x4001300>;
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]18 max-size = <0x400>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100[diff] [blame]19 id = <TB_FW_CONFIG_ID>;
20 };
21
Arunachalam Ganapathyade4a202020-09-22 12:50:45 +0100[diff] [blame]22 tos_fw-config {
23 load-address = <0x0 0x04001700>;
24 max-size = <0x1000>;
25 id = <TOS_FW_CONFIG_ID>;
26 };
27
Usama Arifbec5afd2020-04-17 16:13:39 +0100[diff] [blame]28 hw-config {
Boyan Karatotevbf9ba732023-09-28 13:31:51 +0000[diff] [blame]29 load-address = <0x0 PLAT_HW_CONFIG_DTB_BASE>;
30 max-size = <PLAT_HW_CONFIG_DTB_SIZE>;
Usama Arifbec5afd2020-04-17 16:13:39 +0100[diff] [blame]31 id = <HW_CONFIG_ID>;
32 };
Tamas Banf879bf12023-06-12 11:26:28 +0200[diff] [blame]33 nt_fw-config {
34 load-address = <0x0 (PLAT_HW_CONFIG_DTB_BASE + PLAT_HW_CONFIG_DTB_SIZE)>;
35 max-size = <0x1000>;
36 id = <NT_FW_CONFIG_ID>;
37 };
Usama Arifbec5afd2020-04-17 16:13:39 +0100[diff] [blame]38 };
Usama Arifbec5afd2020-04-17 16:13:39 +0100[diff] [blame]39};