| Chandni Cherukuri | f3a6cab | 2020-09-22 18:56:25 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <lib/cassert.h> |
| 8 | #include <plat/arm/common/plat_arm.h> |
| 9 | |
| 10 | /* Compile time assertion to ensure the core count is 4 */ |
| 11 | CASSERT(PLATFORM_CORE_COUNT == 4U, assert_invalid_platform_core_count); |
| 12 | |
| 13 | /* Topology */ |
| 14 | typedef struct morello_topology { |
| 15 | const unsigned char *power_tree; |
| 16 | unsigned int plat_cluster_core_count; |
| 17 | } morello_topology_t; |
| 18 | |
| 19 | /* |
| 20 | * The power domain tree descriptor. The cluster power domains are |
| 21 | * arranged so that when the PSCI generic code creates the power domain tree, |
| 22 | * the indices of the CPU power domain nodes it allocates match the linear |
| 23 | * indices returned by plat_core_pos_by_mpidr(). |
| 24 | */ |
| 25 | const unsigned char morello_pd_tree_desc[] = { |
| 26 | PLAT_MORELLO_CHIP_COUNT, |
| 27 | PLAT_ARM_CLUSTER_COUNT, |
| 28 | MORELLO_MAX_CPUS_PER_CLUSTER, |
| 29 | MORELLO_MAX_CPUS_PER_CLUSTER, |
| 30 | }; |
| 31 | |
| 32 | /* Topology configuration for morello */ |
| 33 | const morello_topology_t morello_topology = { |
| 34 | .power_tree = morello_pd_tree_desc, |
| 35 | .plat_cluster_core_count = MORELLO_MAX_CPUS_PER_CLUSTER |
| 36 | }; |
| 37 | |
| 38 | /******************************************************************************* |
| 39 | * This function returns the topology tree information. |
| 40 | ******************************************************************************/ |
| 41 | const unsigned char *plat_get_power_domain_tree_desc(void) |
| 42 | { |
| 43 | return morello_topology.power_tree; |
| 44 | } |
| 45 | |
| 46 | /******************************************************************************* |
| 47 | * This function returns the core count within the cluster corresponding to |
| 48 | * `mpidr`. |
| 49 | ******************************************************************************/ |
| 50 | unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) |
| 51 | { |
| 52 | return morello_topology.plat_cluster_core_count; |
| 53 | } |
| 54 | |
| 55 | /******************************************************************************* |
| 56 | * The array mapping platform core position (implemented by plat_my_core_pos()) |
| 57 | * to the SCMI power domain ID implemented by SCP. |
| 58 | ******************************************************************************/ |
| 59 | const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = { |
| 60 | 0, 1, 2, 3}; |