| Khandelwal | 368564c | 2020-01-29 16:51:42 +0000 | [diff] [blame] | 1 | /* |
| Sandrine Bailleux | 7810eb3 | 2022-03-18 12:44:27 +0100 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, Arm Limited. All rights reserved. |
| Khandelwal | 368564c | 2020-01-29 16:51:42 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| Sandrine Bailleux | 7810eb3 | 2022-03-18 12:44:27 +0100 | [diff] [blame] | 7 | #ifndef CORSTONE700_MHU_H |
| 8 | #define CORSTONE700_MHU_H |
| Khandelwal | 368564c | 2020-01-29 16:51:42 +0000 | [diff] [blame] | 9 | |
| 10 | #define MHU_POLL_INTR_STAT_TIMEOUT 50000 /*timeout value in us*/ |
| 11 | |
| 12 | /* CPU MHU secure channel registers */ |
| 13 | #define CPU_INTR_S_STAT 0x00 |
| 14 | #define CPU_INTR_S_SET 0x0C |
| 15 | |
| 16 | /* MHUv2 Control Registers Offsets */ |
| 17 | #define MHU_V2_MSG_CFG_OFFSET 0xF80 |
| 18 | #define MHU_V2_ACCESS_REQ_OFFSET 0xF88 |
| 19 | #define MHU_V2_ACCESS_READY_OFFSET 0xF8C |
| 20 | |
| 21 | #define MHU_V2_ACCESS_REQUEST(addr) \ |
| 22 | mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1) |
| 23 | |
| 24 | #define MHU_V2_CLEAR_REQUEST(addr) \ |
| 25 | mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0) |
| 26 | |
| 27 | #define MHU_V2_IS_ACCESS_READY(addr) \ |
| 28 | (mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1) |
| 29 | |
| 30 | void mhu_secure_message_start(uintptr_t address, unsigned int slot_id); |
| 31 | void mhu_secure_message_send(uintptr_t address, |
| 32 | unsigned int slot_id, |
| 33 | unsigned int message); |
| 34 | void mhu_secure_message_end(uintptr_t address, unsigned int slot_id); |
| 35 | void mhu_secure_init(void); |
| 36 | |
| Sandrine Bailleux | 7810eb3 | 2022-03-18 12:44:27 +0100 | [diff] [blame] | 37 | #endif /* CORSTONE700_MHU_H */ |