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git01.mediatek.com / filogic / atf / 2e74f9ba8cbb86ffb17d64a56a69130fb006b0cc / . / include / drivers / st / stm32mp1_ddr.h
blob: 076566484a722fc782cd9fcb661fe88415e25fac [file] [log] [blame]
Yann Gautiercaf575b2018-07-24 17:18:19 +0200[diff] [blame]1/*
2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7#ifndef _STM32MP1_DDR_H
8#define _STM32MP1_DDR_H
9
10#include <stdbool.h>
11
12#define DT_DDR_COMPAT "st,stm32mp1-ddr"
13
14struct stm32mp1_ddr_size {
15 uint64_t base;
16 uint64_t size;
17};
18
19/**
20 * struct ddr_info
21 *
22 * @dev: pointer for the device
23 * @info: UCLASS RAM information
24 * @ctl: DDR controleur base address
25 * @phy: DDR PHY base address
26 * @syscfg: syscfg base address
27 */
28struct ddr_info {
29 struct stm32mp1_ddr_size info;
30 struct stm32mp1_ddrctl *ctl;
31 struct stm32mp1_ddrphy *phy;
32 uintptr_t pwr;
33 uintptr_t rcc;
34};
35
36struct stm32mp1_ddrctrl_reg {
37 uint32_t mstr;
38 uint32_t mrctrl0;
39 uint32_t mrctrl1;
40 uint32_t derateen;
41 uint32_t derateint;
42 uint32_t pwrctl;
43 uint32_t pwrtmg;
44 uint32_t hwlpctl;
45 uint32_t rfshctl0;
46 uint32_t rfshctl3;
47 uint32_t crcparctl0;
48 uint32_t zqctl0;
49 uint32_t dfitmg0;
50 uint32_t dfitmg1;
51 uint32_t dfilpcfg0;
52 uint32_t dfiupd0;
53 uint32_t dfiupd1;
54 uint32_t dfiupd2;
55 uint32_t dfiphymstr;
56 uint32_t odtmap;
57 uint32_t dbg0;
58 uint32_t dbg1;
59 uint32_t dbgcmd;
60 uint32_t poisoncfg;
61 uint32_t pccfg;
62};
63
64struct stm32mp1_ddrctrl_timing {
65 uint32_t rfshtmg;
66 uint32_t dramtmg0;
67 uint32_t dramtmg1;
68 uint32_t dramtmg2;
69 uint32_t dramtmg3;
70 uint32_t dramtmg4;
71 uint32_t dramtmg5;
72 uint32_t dramtmg6;
73 uint32_t dramtmg7;
74 uint32_t dramtmg8;
75 uint32_t dramtmg14;
76 uint32_t odtcfg;
77};
78
79struct stm32mp1_ddrctrl_map {
80 uint32_t addrmap1;
81 uint32_t addrmap2;
82 uint32_t addrmap3;
83 uint32_t addrmap4;
84 uint32_t addrmap5;
85 uint32_t addrmap6;
86 uint32_t addrmap9;
87 uint32_t addrmap10;
88 uint32_t addrmap11;
89};
90
91struct stm32mp1_ddrctrl_perf {
92 uint32_t sched;
93 uint32_t sched1;
94 uint32_t perfhpr1;
95 uint32_t perflpr1;
96 uint32_t perfwr1;
97 uint32_t pcfgr_0;
98 uint32_t pcfgw_0;
99 uint32_t pcfgqos0_0;
100 uint32_t pcfgqos1_0;
101 uint32_t pcfgwqos0_0;
102 uint32_t pcfgwqos1_0;
103 uint32_t pcfgr_1;
104 uint32_t pcfgw_1;
105 uint32_t pcfgqos0_1;
106 uint32_t pcfgqos1_1;
107 uint32_t pcfgwqos0_1;
108 uint32_t pcfgwqos1_1;
109};
110
111struct stm32mp1_ddrphy_reg {
112 uint32_t pgcr;
113 uint32_t aciocr;
114 uint32_t dxccr;
115 uint32_t dsgcr;
116 uint32_t dcr;
117 uint32_t odtcr;
118 uint32_t zq0cr1;
119 uint32_t dx0gcr;
120 uint32_t dx1gcr;
121 uint32_t dx2gcr;
122 uint32_t dx3gcr;
123};
124
125struct stm32mp1_ddrphy_timing {
126 uint32_t ptr0;
127 uint32_t ptr1;
128 uint32_t ptr2;
129 uint32_t dtpr0;
130 uint32_t dtpr1;
131 uint32_t dtpr2;
132 uint32_t mr0;
133 uint32_t mr1;
134 uint32_t mr2;
135 uint32_t mr3;
136};
137
138struct stm32mp1_ddrphy_cal {
139 uint32_t dx0dllcr;
140 uint32_t dx0dqtr;
141 uint32_t dx0dqstr;
142 uint32_t dx1dllcr;
143 uint32_t dx1dqtr;
144 uint32_t dx1dqstr;
145 uint32_t dx2dllcr;
146 uint32_t dx2dqtr;
147 uint32_t dx2dqstr;
148 uint32_t dx3dllcr;
149 uint32_t dx3dqtr;
150 uint32_t dx3dqstr;
151};
152
153struct stm32mp1_ddr_info {
154 const char *name;
155 uint16_t speed; /* in MHZ */
156 uint32_t size; /* Memory size in byte = col * row * width */
157};
158
159struct stm32mp1_ddr_config {
160 struct stm32mp1_ddr_info info;
161 struct stm32mp1_ddrctrl_reg c_reg;
162 struct stm32mp1_ddrctrl_timing c_timing;
163 struct stm32mp1_ddrctrl_map c_map;
164 struct stm32mp1_ddrctrl_perf c_perf;
165 struct stm32mp1_ddrphy_reg p_reg;
166 struct stm32mp1_ddrphy_timing p_timing;
167 struct stm32mp1_ddrphy_cal p_cal;
168};
169
170int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed);
171void stm32mp1_ddr_init(struct ddr_info *priv,
172 struct stm32mp1_ddr_config *config);
173#endif /* _STM32MP1_DDR_H */