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git01.mediatek.com / filogic / atf / 2e74f9ba8cbb86ffb17d64a56a69130fb006b0cc / . / include / drivers / mmc.h
blob: 0a513bd645c2e1e1c2ce76908251b1796f72537e [file] [log] [blame]
Yann Gautier1e5e85a2018-07-03 18:32:12 +0200[diff] [blame]1/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __MMC_H__
8#define __MMC_H__
9
10#include <stdint.h>
11#include <utils_def.h>
12
13#define MMC_BLOCK_SIZE U(512)
14#define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1))
15#define MMC_BOOT_CLK_RATE (400 * 1000)
16
17#define MMC_CMD(_x) U(_x)
18
19#define MMC_ACMD(_x) U(_x)
20
21#define OCR_POWERUP BIT(31)
22#define OCR_HCS BIT(30)
23#define OCR_BYTE_MODE (U(0) << 29)
24#define OCR_SECTOR_MODE (U(2) << 29)
25#define OCR_ACCESS_MODE_MASK (U(3) << 29)
26#define OCR_3_5_3_6 BIT(23)
27#define OCR_3_4_3_5 BIT(22)
28#define OCR_3_3_3_4 BIT(21)
29#define OCR_3_2_3_3 BIT(20)
30#define OCR_3_1_3_2 BIT(19)
31#define OCR_3_0_3_1 BIT(18)
32#define OCR_2_9_3_0 BIT(17)
33#define OCR_2_8_2_9 BIT(16)
34#define OCR_2_7_2_8 BIT(15)
35#define OCR_VDD_MIN_2V7 GENMASK(23, 15)
36#define OCR_VDD_MIN_2V0 GENMASK(14, 8)
37#define OCR_VDD_MIN_1V7 BIT(7)
38
39#define MMC_RESPONSE_R(_x) U(_x)
40
41/* Value randomly chosen for eMMC RCA, it should be > 1 */
42#define MMC_FIX_RCA 6
43#define RCA_SHIFT_OFFSET 16
44
45#define CMD_EXTCSD_PARTITION_CONFIG 179
46#define CMD_EXTCSD_BUS_WIDTH 183
47#define CMD_EXTCSD_HS_TIMING 185
48#define CMD_EXTCSD_SEC_CNT 212
49
50#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
51#define PART_CFG_PARTITION1_ACCESS (U(1) << 0)
52
53/* Values in EXT CSD register */
54#define MMC_BUS_WIDTH_1 U(0)
55#define MMC_BUS_WIDTH_4 U(1)
56#define MMC_BUS_WIDTH_8 U(2)
57#define MMC_BUS_WIDTH_DDR_4 U(5)
58#define MMC_BUS_WIDTH_DDR_8 U(6)
59#define MMC_BOOT_MODE_BACKWARD (U(0) << 3)
60#define MMC_BOOT_MODE_HS_TIMING (U(1) << 3)
61#define MMC_BOOT_MODE_DDR (U(2) << 3)
62
63#define EXTCSD_SET_CMD (U(0) << 24)
64#define EXTCSD_SET_BITS (U(1) << 24)
65#define EXTCSD_CLR_BITS (U(2) << 24)
66#define EXTCSD_WRITE_BYTES (U(3) << 24)
67#define EXTCSD_CMD(x) (((x) & 0xff) << 16)
68#define EXTCSD_VALUE(x) (((x) & 0xff) << 8)
69#define EXTCSD_CMD_SET_NORMAL U(1)
70
71#define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0)
72#define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3)
73#define CSD_TRAN_SPEED_MULT_SHIFT 3
74
75#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9)
76#define STATUS_READY_FOR_DATA BIT(8)
77#define STATUS_SWITCH_ERROR BIT(7)
78#define MMC_GET_STATE(x) (((x) >> 9) & 0xf)
79#define MMC_STATE_IDLE 0
80#define MMC_STATE_READY 1
81#define MMC_STATE_IDENT 2
82#define MMC_STATE_STBY 3
83#define MMC_STATE_TRAN 4
84#define MMC_STATE_DATA 5
85#define MMC_STATE_RCV 6
86#define MMC_STATE_PRG 7
87#define MMC_STATE_DIS 8
88#define MMC_STATE_BTST 9
89#define MMC_STATE_SLP 10
90
91#define MMC_FLAG_CMD23 (U(1) << 0)
92
93#define CMD8_CHECK_PATTERN U(0xAA)
94#define VHS_2_7_3_6_V BIT(8)
95
96#define SD_SCR_BUS_WIDTH_1 BIT(8)
97#define SD_SCR_BUS_WIDTH_4 BIT(10)
98
99struct mmc_cmd {
100 unsigned int cmd_idx;
101 unsigned int cmd_arg;
102 unsigned int resp_type;
103 unsigned int resp_data[4];
104};
105
106struct mmc_ops {
107 void (*init)(void);
108 int (*send_cmd)(struct mmc_cmd *cmd);
109 int (*set_ios)(unsigned int clk, unsigned int width);
110 int (*prepare)(int lba, uintptr_t buf, size_t size);
111 int (*read)(int lba, uintptr_t buf, size_t size);
112 int (*write)(int lba, const uintptr_t buf, size_t size);
113};
114
115struct mmc_csd_emmc {
116 unsigned int not_used: 1;
117 unsigned int crc: 7;
118 unsigned int ecc: 2;
119 unsigned int file_format: 2;
120 unsigned int tmp_write_protect: 1;
121 unsigned int perm_write_protect: 1;
122 unsigned int copy: 1;
123 unsigned int file_format_grp: 1;
124
125 unsigned int reserved_1: 5;
126 unsigned int write_bl_partial: 1;
127 unsigned int write_bl_len: 4;
128 unsigned int r2w_factor: 3;
129 unsigned int default_ecc: 2;
130 unsigned int wp_grp_enable: 1;
131
132 unsigned int wp_grp_size: 5;
133 unsigned int erase_grp_mult: 5;
134 unsigned int erase_grp_size: 5;
135 unsigned int c_size_mult: 3;
136 unsigned int vdd_w_curr_max: 3;
137 unsigned int vdd_w_curr_min: 3;
138 unsigned int vdd_r_curr_max: 3;
139 unsigned int vdd_r_curr_min: 3;
140 unsigned int c_size_low: 2;
141
142 unsigned int c_size_high: 10;
143 unsigned int reserved_2: 2;
144 unsigned int dsr_imp: 1;
145 unsigned int read_blk_misalign: 1;
146 unsigned int write_blk_misalign: 1;
147 unsigned int read_bl_partial: 1;
148 unsigned int read_bl_len: 4;
149 unsigned int ccc: 12;
150
151 unsigned int tran_speed: 8;
152 unsigned int nsac: 8;
153 unsigned int taac: 8;
154 unsigned int reserved_3: 2;
155 unsigned int spec_vers: 4;
156 unsigned int csd_structure: 2;
157};
158
159struct mmc_csd_sd_v2 {
160 unsigned int not_used: 1;
161 unsigned int crc: 7;
162 unsigned int reserved_1: 2;
163 unsigned int file_format: 2;
164 unsigned int tmp_write_protect: 1;
165 unsigned int perm_write_protect: 1;
166 unsigned int copy: 1;
167 unsigned int file_format_grp: 1;
168
169 unsigned int reserved_2: 5;
170 unsigned int write_bl_partial: 1;
171 unsigned int write_bl_len: 4;
172 unsigned int r2w_factor: 3;
173 unsigned int reserved_3: 2;
174 unsigned int wp_grp_enable: 1;
175
176 unsigned int wp_grp_size: 7;
177 unsigned int sector_size: 7;
178 unsigned int erase_block_en: 1;
179 unsigned int reserved_4: 1;
180 unsigned int c_size_low: 16;
181
182 unsigned int c_size_high: 6;
183 unsigned int reserved_5: 6;
184 unsigned int dsr_imp: 1;
185 unsigned int read_blk_misalign: 1;
186 unsigned int write_blk_misalign: 1;
187 unsigned int read_bl_partial: 1;
188 unsigned int read_bl_len: 4;
189 unsigned int ccc: 12;
190
191 unsigned int tran_speed: 8;
192 unsigned int nsac: 8;
193 unsigned int taac: 8;
194 unsigned int reserved_6: 6;
195 unsigned int csd_structure: 2;
196};
197
198enum mmc_device_type {
199 MMC_IS_EMMC,
200 MMC_IS_SD,
201 MMC_IS_SD_HC,
202};
203
204struct mmc_device_info {
205 unsigned long long device_size; /* Size of device in bytes */
206 unsigned int block_size; /* Block size in bytes */
207 unsigned int max_bus_freq; /* Max bus freq in Hz */
208 enum mmc_device_type mmc_dev_type; /* Type of MMC */
209};
210
Haojian Zhuangd87f0b72018-08-02 14:49:51 +0800[diff] [blame]211size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size);
212size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size);
213size_t mmc_erase_blocks(int lba, size_t size);
214size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
215size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
216size_t mmc_rpmb_erase_blocks(int lba, size_t size);
Yann Gautier1e5e85a2018-07-03 18:32:12 +0200[diff] [blame]217int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
218 unsigned int width, unsigned int flags,
219 struct mmc_device_info *device_info);
220
221#endif /* __MMC_H__ */