blob: 2d7b098377d178db83aacd3298afce2e6a5fd78e [file] [log] [blame]
Andre Przywaraaa26f532017-12-08 01:27:02 +00001/*
Samuel Holland38d98de2019-02-17 15:10:36 -06002 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
Andre Przywaraaa26f532017-12-08 01:27:02 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef SUNXI_MMAP_H
8#define SUNXI_MMAP_H
Andre Przywaraaa26f532017-12-08 01:27:02 +00009
10/* Memory regions */
11#define SUNXI_ROM_BASE 0x00000000
12#define SUNXI_ROM_SIZE 0x00010000
13#define SUNXI_SRAM_BASE 0x00020000
Andre Przywara24b3a1e2018-10-16 00:58:22 +010014#define SUNXI_SRAM_SIZE 0x000f8000
Andre Przywaraaa26f532017-12-08 01:27:02 +000015#define SUNXI_SRAM_A1_BASE 0x00020000
16#define SUNXI_SRAM_A1_SIZE 0x00008000
Samuel Holland38d98de2019-02-17 15:10:36 -060017#define SUNXI_SRAM_A2_BASE 0x00100000
18#define SUNXI_SRAM_A2_SIZE 0x00018000
Andre Przywaraaa26f532017-12-08 01:27:02 +000019#define SUNXI_SRAM_C_BASE 0x00028000
20#define SUNXI_SRAM_C_SIZE 0x0001e000
21#define SUNXI_DEV_BASE 0x01000000
22#define SUNXI_DEV_SIZE 0x09000000
23#define SUNXI_DRAM_BASE 0x40000000
Andre Przywarab3fddff2018-09-20 21:13:55 +010024#define SUNXI_DRAM_VIRT_BASE 0x0a000000
Andre Przywaraaa26f532017-12-08 01:27:02 +000025
26/* Memory-mapped devices */
27#define SUNXI_SYSCON_BASE 0x03000000
28#define SUNXI_CPUCFG_BASE 0x09010000
29#define SUNXI_SID_BASE 0x03006000
30#define SUNXI_DMA_BASE 0x03002000
31#define SUNXI_MSGBOX_BASE 0x03003000
Andre Przywarad878c482020-03-17 00:07:31 +000032#define SUNXI_CCU_BASE 0x03001000
Andre Przywarad878c482020-03-17 00:07:31 +000033#define SUNXI_PIO_BASE 0x0300b000
Samuel Hollandf93a9ab2020-12-13 21:56:15 -060034#define SUNXI_SPC_BASE 0x03008000
Andre Przywaraaa26f532017-12-08 01:27:02 +000035#define SUNXI_TIMER_BASE 0x03009000
36#define SUNXI_WDOG_BASE 0x030090a0
37#define SUNXI_THS_BASE 0x05070400
38#define SUNXI_UART0_BASE 0x05000000
39#define SUNXI_UART1_BASE 0x05000400
40#define SUNXI_UART2_BASE 0x05000800
41#define SUNXI_UART3_BASE 0x05000c00
42#define SUNXI_I2C0_BASE 0x05002000
43#define SUNXI_I2C1_BASE 0x05002400
44#define SUNXI_I2C2_BASE 0x05002800
45#define SUNXI_I2C3_BASE 0x05002c00
46#define SUNXI_SPI0_BASE 0x05010000
47#define SUNXI_SPI1_BASE 0x05011000
48#define SUNXI_SCU_BASE 0x03020000
49#define SUNXI_GICD_BASE 0x03021000
50#define SUNXI_GICC_BASE 0x03022000
51#define SUNXI_R_TIMER_BASE 0x07020000
52#define SUNXI_R_INTC_BASE 0x07021000
53#define SUNXI_R_WDOG_BASE 0x07020400
54#define SUNXI_R_PRCM_BASE 0x07010000
55#define SUNXI_R_TWD_BASE 0x07020800
56#define SUNXI_R_CPUCFG_BASE 0x07000400
57#define SUNXI_R_I2C_BASE 0x07081400
Samuel Hollandcb093f22020-12-13 22:34:10 -060058#define SUNXI_R_RSB_BASE 0x07083000
Andre Przywaraaa26f532017-12-08 01:27:02 +000059#define SUNXI_R_UART_BASE 0x07080000
60#define SUNXI_R_PIO_BASE 0x07022000
61
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000062#endif /* SUNXI_MMAP_H */