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Andrew Thoelke8c28fe02014-06-02 11:40:35 +01001/*
Roberto Vargas05712702018-02-12 12:36:17 +00002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Andrew Thoelke8c28fe02014-06-02 11:40:35 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Andrew Thoelke8c28fe02014-06-02 11:40:35 +01005 */
6
Antonio Nino Diaz9fe40fd2018-10-25 17:11:02 +01007#ifndef CPU_DATA_H
8#define CPU_DATA_H
Andrew Thoelke8c28fe02014-06-02 11:40:35 +01009
Jeenu Viswambharan10a67272017-09-22 08:32:10 +010010#include <ehf.h>
Etienne Carriere97ad6ce2017-09-01 10:22:20 +020011#include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */
12
Soby Mathew748be1d2016-05-05 14:10:46 +010013#ifdef AARCH32
14
15#if CRASH_REPORTING
16#error "Crash reporting is not supported in AArch32"
17#endif
18#define CPU_DATA_CPU_OPS_PTR 0x0
Etienne Carriere97ad6ce2017-09-01 10:22:20 +020019#define CPU_DATA_CRASH_BUF_OFFSET 0x4
Soby Mathew748be1d2016-05-05 14:10:46 +010020
21#else /* AARCH32 */
22
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010023/* Offsets for the cpu_data structure */
Soby Mathew523d6332015-01-08 18:02:19 +000024#define CPU_DATA_CRASH_BUF_OFFSET 0x18
Soby Mathew748be1d2016-05-05 14:10:46 +010025/* need enough space in crash buffer to save 8 registers */
26#define CPU_DATA_CRASH_BUF_SIZE 64
27#define CPU_DATA_CPU_OPS_PTR 0x10
28
29#endif /* AARCH32 */
30
Soby Mathewc1adbbc2014-06-25 10:07:40 +010031#if CRASH_REPORTING
dp-arm3cac7862016-09-19 11:18:44 +010032#define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \
33 CPU_DATA_CRASH_BUF_SIZE)
Soby Mathewc1adbbc2014-06-25 10:07:40 +010034#else
dp-arm3cac7862016-09-19 11:18:44 +010035#define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET
Soby Mathewc1adbbc2014-06-25 10:07:40 +010036#endif
Soby Mathewc704cbc2014-08-14 11:33:56 +010037
Etienne Carriere97ad6ce2017-09-01 10:22:20 +020038/* cpu_data size is the data size rounded up to the platform cache line size */
39#define CPU_DATA_SIZE (((CPU_DATA_CRASH_BUF_END + \
40 CACHE_WRITEBACK_GRANULE - 1) / \
41 CACHE_WRITEBACK_GRANULE) * \
42 CACHE_WRITEBACK_GRANULE)
43
dp-arm3cac7862016-09-19 11:18:44 +010044#if ENABLE_RUNTIME_INSTRUMENTATION
45/* Temporary space to store PMF timestamps from assembly code */
46#define CPU_DATA_PMF_TS_COUNT 1
47#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END
48#define CPU_DATA_PMF_TS0_IDX 0
49#endif
50
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010051#ifndef __ASSEMBLY__
52
53#include <arch_helpers.h>
Soby Mathew523d6332015-01-08 18:02:19 +000054#include <cassert.h>
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010055#include <platform_def.h>
Achin Guptaf3ccbab2014-07-25 14:52:47 +010056#include <psci.h>
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010057#include <stdint.h>
58
Soby Mathew523d6332015-01-08 18:02:19 +000059/* Offsets for the cpu_data structure */
60#define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\
61 (cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info)
62
63#if PLAT_PCPU_DATA_SIZE
64#define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\
65 (cpu_data_t, platform_cpu_data)
66#endif
67
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010068/*******************************************************************************
69 * Function & variable prototypes
70 ******************************************************************************/
71
72/*******************************************************************************
73 * Cache of frequently used per-cpu data:
Andrew Thoelkec02dbd62014-06-02 10:00:25 +010074 * Pointers to non-secure and secure security state contexts
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010075 * Address of the crash stack
76 * It is aligned to the cache line boundary to allow efficient concurrent
77 * manipulation of these pointers on different cpus
78 *
79 * TODO: Add other commonly used variables to this (tf_issues#90)
80 *
81 * The data structure and the _cpu_data accessors should not be used directly
82 * by components that have per-cpu members. The member access macros should be
83 * used for this.
84 ******************************************************************************/
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010085typedef struct cpu_data {
Soby Mathew748be1d2016-05-05 14:10:46 +010086#ifndef AARCH32
Andrew Thoelkec02dbd62014-06-02 10:00:25 +010087 void *cpu_context[2];
Soby Mathew748be1d2016-05-05 14:10:46 +010088#endif
Soby Mathewa0fedc42016-06-16 14:52:04 +010089 uintptr_t cpu_ops_ptr;
Soby Mathewc1adbbc2014-06-25 10:07:40 +010090#if CRASH_REPORTING
Soby Mathewa0fedc42016-06-16 14:52:04 +010091 u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
Soby Mathewc1adbbc2014-06-25 10:07:40 +010092#endif
dp-arm3cac7862016-09-19 11:18:44 +010093#if ENABLE_RUNTIME_INSTRUMENTATION
94 uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT];
95#endif
Soby Mathew523d6332015-01-08 18:02:19 +000096 struct psci_cpu_data psci_svc_cpu_data;
97#if PLAT_PCPU_DATA_SIZE
98 uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE];
99#endif
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100100#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
101 pe_exc_data_t ehf_data;
102#endif
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100103} __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t;
104
Roberto Vargas05712702018-02-12 12:36:17 +0000105extern cpu_data_t percpu_data[PLATFORM_CORE_COUNT];
106
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100107#if CRASH_REPORTING
108/* verify assembler offsets match data structures */
109CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof
110 (cpu_data_t, crash_buf),
111 assert_cpu_data_crash_stack_offset_mismatch);
112#endif
113
Etienne Carriere97ad6ce2017-09-01 10:22:20 +0200114CASSERT(CPU_DATA_SIZE == sizeof(cpu_data_t),
115 assert_cpu_data_size_mismatch);
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100116
Soby Mathewc704cbc2014-08-14 11:33:56 +0100117CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof
118 (cpu_data_t, cpu_ops_ptr),
119 assert_cpu_data_cpu_ops_ptr_offset_mismatch);
120
dp-arm3cac7862016-09-19 11:18:44 +0100121#if ENABLE_RUNTIME_INSTRUMENTATION
122CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof
123 (cpu_data_t, cpu_data_pmf_ts[0]),
124 assert_cpu_data_pmf_ts0_offset_mismatch);
125#endif
126
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100127struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100128
Soby Mathew748be1d2016-05-05 14:10:46 +0100129#ifndef AARCH32
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100130/* Return the cpu_data structure for the current CPU. */
131static inline struct cpu_data *_cpu_data(void)
132{
133 return (cpu_data_t *)read_tpidr_el3();
134}
Soby Mathew748be1d2016-05-05 14:10:46 +0100135#else
136struct cpu_data *_cpu_data(void);
137#endif
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100138
139/**************************************************************************
140 * APIs for initialising and accessing per-cpu data
141 *************************************************************************/
142
143void init_cpu_data_ptr(void);
Vikram Kanigiri9b38fc82015-01-29 18:27:38 +0000144void init_cpu_ops(void);
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100145
146#define get_cpu_data(_m) _cpu_data()->_m
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000147#define set_cpu_data(_m, _v) _cpu_data()->_m = (_v)
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100148#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000149#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = (_v)
Joel Hutton43a4d572017-10-20 10:31:14 +0100150/* ((cpu_data_t *)0)->_m is a dummy to get the sizeof the struct member _m */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100151#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \
Joel Hutton43a4d572017-10-20 10:31:14 +0100152 &(_cpu_data()->_m), \
153 sizeof(((cpu_data_t *)0)->_m))
Soby Mathew24ab34f2016-05-03 17:11:42 +0100154#define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \
Joel Hutton43a4d572017-10-20 10:31:14 +0100155 &(_cpu_data()->_m), \
156 sizeof(((cpu_data_t *)0)->_m))
Soby Mathew7d861ea2014-11-18 10:14:14 +0000157#define flush_cpu_data_by_index(_ix, _m) \
Soby Mathewa0fedc42016-06-16 14:52:04 +0100158 flush_dcache_range((uintptr_t) \
Soby Mathew7d861ea2014-11-18 10:14:14 +0000159 &(_cpu_data_by_index(_ix)->_m), \
Joel Hutton43a4d572017-10-20 10:31:14 +0100160 sizeof(((cpu_data_t *)0)->_m))
Achin Guptae4b9fa42014-07-25 14:47:05 +0100161
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100162
163#endif /* __ASSEMBLY__ */
Antonio Nino Diaz9fe40fd2018-10-25 17:11:02 +0100164#endif /* CPU_DATA_H */