Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / 2dfe1d0dd064a2ba40aee4af98215694b7a59f46 / . / include / drivers / st / stm32mp1_ddr.h
blob: 363e3020c26d2ac81d54baf37afc7426c457127a [file] [log] [blame]
Yann Gautiercaf575b2018-07-24 17:18:19 +0200[diff] [blame]1/*
2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef STM32MP1_DDR_H
8#define STM32MP1_DDR_H
Yann Gautiercaf575b2018-07-24 17:18:19 +0200[diff] [blame]9
10#include <stdbool.h>
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]11#include <stdint.h>
Yann Gautiercaf575b2018-07-24 17:18:19 +0200[diff] [blame]12
13#define DT_DDR_COMPAT "st,stm32mp1-ddr"
14
15struct stm32mp1_ddr_size {
16 uint64_t base;
17 uint64_t size;
18};
19
20/**
21 * struct ddr_info
22 *
23 * @dev: pointer for the device
24 * @info: UCLASS RAM information
25 * @ctl: DDR controleur base address
26 * @phy: DDR PHY base address
27 * @syscfg: syscfg base address
28 */
29struct ddr_info {
30 struct stm32mp1_ddr_size info;
31 struct stm32mp1_ddrctl *ctl;
32 struct stm32mp1_ddrphy *phy;
33 uintptr_t pwr;
34 uintptr_t rcc;
35};
36
37struct stm32mp1_ddrctrl_reg {
38 uint32_t mstr;
39 uint32_t mrctrl0;
40 uint32_t mrctrl1;
41 uint32_t derateen;
42 uint32_t derateint;
43 uint32_t pwrctl;
44 uint32_t pwrtmg;
45 uint32_t hwlpctl;
46 uint32_t rfshctl0;
47 uint32_t rfshctl3;
48 uint32_t crcparctl0;
49 uint32_t zqctl0;
50 uint32_t dfitmg0;
51 uint32_t dfitmg1;
52 uint32_t dfilpcfg0;
53 uint32_t dfiupd0;
54 uint32_t dfiupd1;
55 uint32_t dfiupd2;
56 uint32_t dfiphymstr;
57 uint32_t odtmap;
58 uint32_t dbg0;
59 uint32_t dbg1;
60 uint32_t dbgcmd;
61 uint32_t poisoncfg;
62 uint32_t pccfg;
63};
64
65struct stm32mp1_ddrctrl_timing {
66 uint32_t rfshtmg;
67 uint32_t dramtmg0;
68 uint32_t dramtmg1;
69 uint32_t dramtmg2;
70 uint32_t dramtmg3;
71 uint32_t dramtmg4;
72 uint32_t dramtmg5;
73 uint32_t dramtmg6;
74 uint32_t dramtmg7;
75 uint32_t dramtmg8;
76 uint32_t dramtmg14;
77 uint32_t odtcfg;
78};
79
80struct stm32mp1_ddrctrl_map {
81 uint32_t addrmap1;
82 uint32_t addrmap2;
83 uint32_t addrmap3;
84 uint32_t addrmap4;
85 uint32_t addrmap5;
86 uint32_t addrmap6;
87 uint32_t addrmap9;
88 uint32_t addrmap10;
89 uint32_t addrmap11;
90};
91
92struct stm32mp1_ddrctrl_perf {
93 uint32_t sched;
94 uint32_t sched1;
95 uint32_t perfhpr1;
96 uint32_t perflpr1;
97 uint32_t perfwr1;
98 uint32_t pcfgr_0;
99 uint32_t pcfgw_0;
100 uint32_t pcfgqos0_0;
101 uint32_t pcfgqos1_0;
102 uint32_t pcfgwqos0_0;
103 uint32_t pcfgwqos1_0;
104 uint32_t pcfgr_1;
105 uint32_t pcfgw_1;
106 uint32_t pcfgqos0_1;
107 uint32_t pcfgqos1_1;
108 uint32_t pcfgwqos0_1;
109 uint32_t pcfgwqos1_1;
110};
111
112struct stm32mp1_ddrphy_reg {
113 uint32_t pgcr;
114 uint32_t aciocr;
115 uint32_t dxccr;
116 uint32_t dsgcr;
117 uint32_t dcr;
118 uint32_t odtcr;
119 uint32_t zq0cr1;
120 uint32_t dx0gcr;
121 uint32_t dx1gcr;
122 uint32_t dx2gcr;
123 uint32_t dx3gcr;
124};
125
126struct stm32mp1_ddrphy_timing {
127 uint32_t ptr0;
128 uint32_t ptr1;
129 uint32_t ptr2;
130 uint32_t dtpr0;
131 uint32_t dtpr1;
132 uint32_t dtpr2;
133 uint32_t mr0;
134 uint32_t mr1;
135 uint32_t mr2;
136 uint32_t mr3;
137};
138
139struct stm32mp1_ddrphy_cal {
140 uint32_t dx0dllcr;
141 uint32_t dx0dqtr;
142 uint32_t dx0dqstr;
143 uint32_t dx1dllcr;
144 uint32_t dx1dqtr;
145 uint32_t dx1dqstr;
146 uint32_t dx2dllcr;
147 uint32_t dx2dqtr;
148 uint32_t dx2dqstr;
149 uint32_t dx3dllcr;
150 uint32_t dx3dqtr;
151 uint32_t dx3dqstr;
152};
153
154struct stm32mp1_ddr_info {
155 const char *name;
156 uint16_t speed; /* in MHZ */
157 uint32_t size; /* Memory size in byte = col * row * width */
158};
159
160struct stm32mp1_ddr_config {
161 struct stm32mp1_ddr_info info;
162 struct stm32mp1_ddrctrl_reg c_reg;
163 struct stm32mp1_ddrctrl_timing c_timing;
164 struct stm32mp1_ddrctrl_map c_map;
165 struct stm32mp1_ddrctrl_perf c_perf;
166 struct stm32mp1_ddrphy_reg p_reg;
167 struct stm32mp1_ddrphy_timing p_timing;
168 struct stm32mp1_ddrphy_cal p_cal;
169};
170
171int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed);
172void stm32mp1_ddr_init(struct ddr_info *priv,
173 struct stm32mp1_ddr_config *config);
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]174#endif /* STM32MP1_DDR_H */