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Dan Handleycc573cb2018-03-14 13:01:39 +00001Trusted Firmware-A - version 1.5
Dan Handley610e7e12018-03-01 18:44:00 +00002================================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) provides a reference implementation of secure world
Dan Handleycc573cb2018-03-14 13:01:39 +00005software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
6at Exception Level 3 (EL3). It implements various Arm interface standards,
7such as:
Dan Handleyed09d382017-07-05 17:40:29 +01008
9- The `Power State Coordination Interface (PSCI)`_
Dan Handley610e7e12018-03-01 18:44:00 +000010- Trusted Board Boot Requirements (TBBR, Arm DEN0006C-1)
Dan Handleyed09d382017-07-05 17:40:29 +010011- `SMC Calling Convention`_
12- `System Control and Management Interface`_
Dan Handleycc573cb2018-03-14 13:01:39 +000013- `Software Delegated Exception Interface (SDEI)`_
Dan Handleyed09d382017-07-05 17:40:29 +010014
Dan Handleycc573cb2018-03-14 13:01:39 +000015Where possible, the code is designed for reuse or porting to other Armv7-A and
16Armv8-A model and hardware platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010017
Dan Handley610e7e12018-03-01 18:44:00 +000018Arm will continue development in collaboration with interested parties to
19provide a full reference implementation of Secure Monitor code and Arm standards
Dan Handleycc573cb2018-03-14 13:01:39 +000020to the benefit of all developers working with Armv7-A and Armv8-A TrustZone
21technology.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022
23License
24-------
25
26The software is provided under a BSD-3-Clause `license`_. Contributions to this
27project are accepted under the same license with developer sign-off as
28described in the `Contributing Guidelines`_.
29
30This project contains code from other projects as listed below. The original
31license text is included in those source files.
32
Dan Handley4463db82017-07-17 15:19:37 +010033- The stdlib source code is derived from FreeBSD code, which uses various
34 BSD licenses, including BSD-3-Clause and BSD-2-Clause.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010035
Dan Handley5274dc22018-07-25 16:42:10 +010036- The libfdt source code is disjunctively dual licensed
37 (GPL-2.0+ OR BSD-2-Clause). It is used by this project under the terms of
38 the BSD-2-Clause license. Any contributions to this code must be made under
39 the terms of both licenses.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010040
Dan Handley5274dc22018-07-25 16:42:10 +010041- The LLVM compiler-rt source code is disjunctively dual licensed
42 (NCSA OR MIT). It is used by this project under the terms of the NCSA
43 license (also known as the University of Illinois/NCSA Open Source License),
44 which is a permissive license compatible with BSD-3-Clause. Any
45 contributions to this code must be made under the terms of both licenses.
Dan Handleyed09d382017-07-05 17:40:29 +010046
Dan Handleycc573cb2018-03-14 13:01:39 +000047- The zlib source code is licensed under the Zlib license, which is a
48 permissive license compatible with BSD-3-Clause.
49
Dan Handley5274dc22018-07-25 16:42:10 +010050- Some STMicroelectronics platform source code is disjunctively dual licensed
51 (GPL-2.0+ OR BSD-3-Clause). It is used by this project under the terms of the
52 BSD-3-Clause license. Any contributions to this code must be made under the
53 terms of both licenses.
54
Dan Handleycc573cb2018-03-14 13:01:39 +000055This release
Douglas Raillardd7c21b72017-06-28 15:23:03 +010056------------
57
58This release provides a suitable starting point for productization of secure
Dan Handleyed09d382017-07-05 17:40:29 +010059world boot and runtime firmware, in either the AArch32 or AArch64 execution
60state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010061
62Users are encouraged to do their own security validation, including penetration
Dan Handley610e7e12018-03-01 18:44:00 +000063testing, on any secure world code derived from TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010064
65Functionality
66~~~~~~~~~~~~~
67
Dan Handleyed09d382017-07-05 17:40:29 +010068- Initialization of the secure world, for example exception vectors, control
69 registers and interrupts for the platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010070
71- Library support for CPU specific reset and power down sequences. This
Dan Handley610e7e12018-03-01 18:44:00 +000072 includes support for errata workarounds and the latest Arm DynamIQ CPUs.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010073
Dan Handley610e7e12018-03-01 18:44:00 +000074- Drivers to enable standard initialization of Arm System IP, for example
Dan Handleyed09d382017-07-05 17:40:29 +010075 Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
76 Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
77 Controller (TZC).
Douglas Raillardd7c21b72017-06-28 15:23:03 +010078
Dan Handleyed09d382017-07-05 17:40:29 +010079- A generic `SCMI`_ driver to interface with conforming power controllers, for
Dan Handley610e7e12018-03-01 18:44:00 +000080 example the Arm System Control Processor (SCP).
Douglas Raillardd7c21b72017-06-28 15:23:03 +010081
Dan Handleyed09d382017-07-05 17:40:29 +010082- SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
83 Convention`_ using an EL3 runtime services framework.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010084
Dan Handleyed09d382017-07-05 17:40:29 +010085- `PSCI`_ library support for CPU, cluster and system power management
86 use-cases.
87 This library is pre-integrated with the AArch64 EL3 Runtime Software, and
88 is also suitable for integration with other AArch32 EL3 Runtime Software,
89 for example an AArch32 Secure OS.
90
91- A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library
92 integration with AArch32 EL3 Runtime Software.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010093
94- Secure Monitor library code such as world switching, EL1 context management
95 and interrupt routing.
Dan Handleyed09d382017-07-05 17:40:29 +010096 When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
97 AArch64 EL3 Runtime Software must be integrated with a dispatcher component
98 (SPD) to customize the interaction with the SP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010099
Dan Handleyed09d382017-07-05 17:40:29 +0100100- A Test SP/SPD to demonstrate AArch64 Secure Monitor functionality and SP
101 interaction with PSCI.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100102
Dan Handleyed09d382017-07-05 17:40:29 +0100103- SPDs for the `OP-TEE Secure OS`_, `NVidia Trusted Little Kernel`_
104 and `Trusty Secure OS`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100105
106- A Trusted Board Boot implementation, conforming to all mandatory TBBR
Dan Handleyed09d382017-07-05 17:40:29 +0100107 requirements. This includes image authentication, Firmware Update (or
108 recovery mode), and packaging of the various firmware images into a
109 Firmware Image Package (FIP).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100110
Dan Handleycc573cb2018-03-14 13:01:39 +0000111- Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
112 its hardware Root of Trust and crypto acceleration services.
113
114- Reliability, Availability, and Serviceability (RAS) functionality, including
115
116 - A Secure Partition Manager (SPM) to manage Secure Partitions in
117 Secure-EL0, which can be used to implement simple management and
118 security services.
119
120 - An SDEI dispatcher to route interrupt-based SDEI events.
121
122 - An Exception Handling Framework (EHF) that allows dispatching of EL3
123 interrupts to their registered handlers, to facilitate firmware-first
124 error handling.
125
126- A dynamic configuration framework that enables each of the firmware images
127 to be configured at runtime if required by the platform. It also enables
128 loading of a hardware configuration (for example, a kernel device tree)
129 as part of the FIP, to be passed through the firmware stages.
Dan Handleyed09d382017-07-05 17:40:29 +0100130
131- Support for alternative boot flows, for example to support platforms where
132 the EL3 Runtime Software is loaded using other firmware or a separate
Dan Handleycc573cb2018-03-14 13:01:39 +0000133 secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
134 at EL3.
Dan Handleyed09d382017-07-05 17:40:29 +0100135
Dan Handley610e7e12018-03-01 18:44:00 +0000136- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100137
138For a full description of functionality and implementation details, please
139see the `Firmware Design`_ and supporting documentation. The `Change Log`_
140provides details of changes made since the last release.
141
142Platforms
143~~~~~~~~~
144
Dan Handleyed09d382017-07-05 17:40:29 +0100145Various AArch32 and AArch64 builds of this release has been tested on variants
Dan Handley610e7e12018-03-01 18:44:00 +0000146r0, r1 and r2 of the `Juno Arm Development Platform`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100147
Dan Handley610e7e12018-03-01 18:44:00 +0000148Various AArch64 builds of this release have been tested on the following Arm
Dan Handleycc573cb2018-03-14 13:01:39 +0000149Fixed Virtual Platforms (`FVP`_) without shifted affinities, and that do not
150support threaded CPU cores (64-bit host machine only):
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100151
Dan Handleycc573cb2018-03-14 13:01:39 +0000152NOTE: Unless otherwise stated, the FVP Version is 11.2 Build 11.2.33.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100153
Dan Handleyed09d382017-07-05 17:40:29 +0100154- ``Foundation_Platform``
Dan Handleycc573cb2018-03-14 13:01:39 +0000155- ``FVP_Base_AEMv8A-AEMv8A`` (and also Version 9.0, Build 0.8.9005)
Dan Handleyed09d382017-07-05 17:40:29 +0100156- ``FVP_Base_Cortex-A35x4``
157- ``FVP_Base_Cortex-A53x4``
158- ``FVP_Base_Cortex-A57x4-A53x4``
159- ``FVP_Base_Cortex-A57x4``
160- ``FVP_Base_Cortex-A72x4-A53x4``
161- ``FVP_Base_Cortex-A72x4``
162- ``FVP_Base_Cortex-A73x4-A53x4``
163- ``FVP_Base_Cortex-A73x4``
Dan Handleycc573cb2018-03-14 13:01:39 +0000164
165Additionally, various AArch64 builds were tested on the following Arm `FVP`_ s
166with shifted affinities, supporting threaded CPU cores (64-bit host machine
167only).
168
169- ``FVP_Base_Cortex-A55x4-A75x4`` (Version 0.0, build 0.0.4395)
170- ``FVP_Base_Cortex-A55x4`` (Version 0.0, build 0.0.4395)
171- ``FVP_Base_Cortex-A75x4`` (Version 0.0, build 0.0.4395)
172- ``FVP_Base_RevC-2xAEMv8A``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100173
Dan Handley610e7e12018-03-01 18:44:00 +0000174Various AArch32 builds of this release has been tested on the following Arm
Dan Handleycc573cb2018-03-14 13:01:39 +0000175`FVP`_\ s without shifted affinities, and that do not support threaded CPU cores
176(64-bit host machine only):
Dan Handleyed09d382017-07-05 17:40:29 +0100177
Dan Handleycc573cb2018-03-14 13:01:39 +0000178- ``FVP_Base_AEMv8A-AEMv8A``
Dan Handleyed09d382017-07-05 17:40:29 +0100179- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100180
181The Foundation FVP can be downloaded free of charge. The Base FVPs can be
Dan Handley610e7e12018-03-01 18:44:00 +0000182licensed from Arm. See the `Arm FVP website`_.
Dan Handleyed09d382017-07-05 17:40:29 +0100183
Dan Handleycc573cb2018-03-14 13:01:39 +0000184All the above platforms have been tested with `Linaro Release 17.10`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100185
186This release also contains the following platform support:
187
Dan Handleycc573cb2018-03-14 13:01:39 +0000188- HiKey, HiKey960 and Poplar boards
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100189- MediaTek MT6795 and MT8173 SoCs
Dan Handleyed09d382017-07-05 17:40:29 +0100190- NVidia T132, T186 and T210 SoCs
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100191- QEMU emulator
Dan Handleycc573cb2018-03-14 13:01:39 +0000192- Raspberry Pi 3 board
Dan Handleyed09d382017-07-05 17:40:29 +0100193- RockChip RK3328, RK3368 and RK3399 SoCs
Sumit Garg760c1d32018-06-21 11:28:18 +0530194- Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs
Nishanth Menon0192f892016-10-14 01:13:34 +0000195- Texas Instruments K3 SoCs
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100196- Xilinx Zynq UltraScale + MPSoC
197
Dan Handleycc573cb2018-03-14 13:01:39 +0000198Still to come
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100199~~~~~~~~~~~~~
200
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100201- More platform support.
202
Dan Handleycc573cb2018-03-14 13:01:39 +0000203- Improved dynamic configuration support.
204
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100205- Ongoing support for new architectural features, CPUs and System IP.
206
Dan Handleycc573cb2018-03-14 13:01:39 +0000207- Ongoing support for new Arm system architecture specifications.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100208
209- Ongoing security hardening, optimization and quality improvements.
210
Dan Handleyed09d382017-07-05 17:40:29 +0100211For a full list of detailed issues in the current code, please see the `Change
212Log`_ and the `GitHub issue tracker`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100213
Dan Handleycc573cb2018-03-14 13:01:39 +0000214Getting started
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100215---------------
216
Dan Handley610e7e12018-03-01 18:44:00 +0000217Get the TF-A source code from `GitHub`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100218
219See the `User Guide`_ for instructions on how to install, build and use
Dan Handley610e7e12018-03-01 18:44:00 +0000220the TF-A with the Arm `FVP`_\ s.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100221
Dan Handley610e7e12018-03-01 18:44:00 +0000222See the `Firmware Design`_ for information on how the TF-A works.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100223
224See the `Porting Guide`_ as well for information about how to use this
Dan Handleycc573cb2018-03-14 13:01:39 +0000225software on another Armv7-A or Armv8-A platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100226
227See the `Contributing Guidelines`_ for information on how to contribute to this
228project and the `Acknowledgments`_ file for a list of contributors to the
229project.
230
Dimitris Papastamosfc62ebd2018-07-30 15:38:04 +0100231IRC channel
232~~~~~~~~~~~
233
234Development discussion takes place on the #trusted-firmware-a channel
235on the Freenode IRC network. This is not an official support channel.
236If you have an issue to raise, please use the `GitHub issue tracker`_.
237
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100238Feedback and support
239~~~~~~~~~~~~~~~~~~~~
240
Dan Handley610e7e12018-03-01 18:44:00 +0000241Arm welcomes any feedback on TF-A. If you think you have found a security
242vulnerability, please report this using the process defined in the TF-A
243`Security Centre`_. For all other feedback, please use the
Dan Handleyed09d382017-07-05 17:40:29 +0100244`GitHub issue tracker`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100245
Dan Handley610e7e12018-03-01 18:44:00 +0000246Arm licensees may contact Arm directly via their partner managers.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100247
248--------------
249
Dan Handley610e7e12018-03-01 18:44:00 +0000250*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100251
Dan Handleycc573cb2018-03-14 13:01:39 +0000252.. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100253.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
Dan Handleyed09d382017-07-05 17:40:29 +0100254.. _Power State Coordination Interface (PSCI): PSCI_
255.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
256.. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
257.. _System Control and Management Interface: SCMI_
258.. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
danh-arm190e4fa2018-03-20 17:01:39 +0000259.. _Software Delegated Exception Interface (SDEI): SDEI_
Dan Handleycc573cb2018-03-14 13:01:39 +0000260.. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
Dan Handley610e7e12018-03-01 18:44:00 +0000261.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
262.. _Arm FVP website: FVP_
Dan Handleyed09d382017-07-05 17:40:29 +0100263.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Dan Handleycc573cb2018-03-14 13:01:39 +0000264.. _Linaro Release 17.10: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease17.10
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100265.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
266.. _NVidia Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
Dan Handleyed09d382017-07-05 17:40:29 +0100267.. _Trusty Secure OS: https://source.android.com/security/trusty
268.. _GitHub: https://www.github.com/ARM-software/arm-trusted-firmware
269.. _GitHub issue tracker: https://github.com/ARM-software/tf-issues/issues
270.. _Security Centre: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Security-Centre
271.. _license: ./license.rst
272.. _Contributing Guidelines: ./contributing.rst
273.. _Acknowledgments: ./acknowledgements.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100274.. _Firmware Design: ./docs/firmware-design.rst
275.. _Change Log: ./docs/change-log.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100276.. _User Guide: ./docs/user-guide.rst
277.. _Porting Guide: ./docs/porting-guide.rst