Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 1 | Allwinner ARMv8 SoCs |
| 2 | ==================== |
Samuel Holland | 7438320 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 3 | |
| 4 | Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Allwinner |
| 5 | SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and |
| 6 | PSCI runtime services. |
Andre Przywara | 4416ba8 | 2018-06-22 00:33:28 +0100 | [diff] [blame] | 7 | |
Andre Przywara | 928fc87 | 2020-12-11 21:29:31 +0000 | [diff] [blame] | 8 | Building TF-A |
| 9 | ------------- |
Andre Przywara | 4416ba8 | 2018-06-22 00:33:28 +0100 | [diff] [blame] | 10 | |
Andre Przywara | 928fc87 | 2020-12-11 21:29:31 +0000 | [diff] [blame] | 11 | To build for machines with an A64 or H5 SoC: |
| 12 | |
| 13 | .. code:: shell |
| 14 | |
| 15 | make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31 |
| 16 | |
| 17 | To build for machines with an H6 SoC: |
| 18 | |
| 19 | .. code:: shell |
| 20 | |
| 21 | make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31 |
Samuel Holland | 7438320 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 22 | |
Andre Przywara | 2d42e5f | 2020-11-28 01:39:17 +0000 | [diff] [blame^] | 23 | To build for machines with an H616 or H313 SoC: |
| 24 | |
| 25 | .. code:: shell |
| 26 | |
| 27 | make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h616 DEBUG=1 bl31 |
| 28 | |
Samuel Holland | 7438320 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 29 | |
Andre Przywara | 928fc87 | 2020-12-11 21:29:31 +0000 | [diff] [blame] | 30 | Installation |
| 31 | ------------ |
| 32 | |
| 33 | U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot). |
| 34 | Loading is done from SD card, eMMC or SPI flash, also via an USB debug |
| 35 | interface (FEL). |
Samuel Holland | 7438320 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 36 | |
| 37 | After building bl31.bin, the binary must be fed to the U-Boot build system |
| 38 | to include it in the FIT image that the SPL loader will process. |
| 39 | bl31.bin can be either copied (or sym-linked) into U-Boot's root directory, |
| 40 | or the environment variable BL31 must contain the binary's path. |
| 41 | See the respective `U-Boot documentation`_ for more details. |
| 42 | |
Andre Przywara | 928fc87 | 2020-12-11 21:29:31 +0000 | [diff] [blame] | 43 | .. _U-Boot documentation: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/sunxi/README.sunxi64 |
Samuel Holland | 7438320 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 44 | |
Andre Przywara | 928fc87 | 2020-12-11 21:29:31 +0000 | [diff] [blame] | 45 | Memory layout |
| 46 | ------------- |
Samuel Holland | 7438320 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 47 | |
Andre Przywara | 928fc87 | 2020-12-11 21:29:31 +0000 | [diff] [blame] | 48 | A64, H5 and H6 SoCs |
| 49 | ~~~~~~~~~~~~~~~~~~~ |
Samuel Holland | 7438320 | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 50 | |
Andre Przywara | 928fc87 | 2020-12-11 21:29:31 +0000 | [diff] [blame] | 51 | BL31 lives in SRAM A2, which is documented to be accessible from secure |
| 52 | world only. Since this SRAM region is very limited (48 KB), we take |
| 53 | several measures to reduce memory consumption. One of them is to confine |
| 54 | BL31 to only 28 bits of virtual address space, which reduces the number |
| 55 | of required page tables (each occupying 4KB of memory). |
| 56 | The mapping we use on those SoCs is as follows: |
Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 57 | |
Andre Przywara | 928fc87 | 2020-12-11 21:29:31 +0000 | [diff] [blame] | 58 | :: |
Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 59 | |
Andre Przywara | 928fc87 | 2020-12-11 21:29:31 +0000 | [diff] [blame] | 60 | 0 64K 16M 1GB 1G+160M physical address |
| 61 | +-+------+-+---+------+--...---+-------+----+------+---------- |
| 62 | |B| |S|///| |//...///| |////| | |
| 63 | |R| SRAM |C|///| dev |//...///| (sec) |////| BL33 | DRAM ... |
| 64 | |O| |P|///| MMIO |//...///| DRAM |////| | |
| 65 | |M| | |///| |//...///| (32M) |////| | |
| 66 | +-+------+-+---+------+--...---+-------+----+------+---------- |
| 67 | | | | | | | / / / / |
| 68 | | | | | | | / / / / |
| 69 | | | | | | | / / / / |
| 70 | | | | | | | / // / |
| 71 | | | | | | | / / / |
| 72 | +-+------+-+---+------+--+-------+------+ |
| 73 | |B| |S|///| |//| | | |
| 74 | |R| SRAM |C|///| dev |//| sec | BL33 | |
| 75 | |O| |P|///| MMIO |//| DRAM | | |
| 76 | |M| | |///| |//| | | |
| 77 | +-+------+-+---+------+--+-------+------+ |
| 78 | 0 64K 16M 160M 192M 256M virtual address |
Andre Przywara | aa26f53 | 2017-12-08 01:27:02 +0000 | [diff] [blame] | 79 | |
Amit Singh Tomar | 2f37224 | 2018-06-20 00:44:50 +0530 | [diff] [blame] | 80 | |
Andre Przywara | 2d42e5f | 2020-11-28 01:39:17 +0000 | [diff] [blame^] | 81 | H616 SoC |
| 82 | ~~~~~~~~ |
| 83 | |
| 84 | The H616 lacks the secure SRAM region present on the other SoCs, also |
| 85 | lacks the "ARISC" management processor (SCP) we use. BL31 thus needs to |
| 86 | run from DRAM, which prevents our compressed virtual memory map described |
| 87 | above. Since running in DRAM also lifts the restriction of the limited |
| 88 | SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual |
| 89 | address space. So the virtual addresses used in BL31 match the physical |
| 90 | addresses as presented above. |
| 91 | |
Amit Singh Tomar | 2f37224 | 2018-06-20 00:44:50 +0530 | [diff] [blame] | 92 | Trusted OS dispatcher |
Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 93 | --------------------- |
Amit Singh Tomar | 2f37224 | 2018-06-20 00:44:50 +0530 | [diff] [blame] | 94 | |
| 95 | One can boot Trusted OS(OP-TEE OS, bl32 image) along side bl31 image on Allwinner A64. |
| 96 | |
| 97 | In order to include the 'opteed' dispatcher in the image, pass 'SPD=opteed' on the command line |
| 98 | while compiling the bl31 image and make sure the loader (SPL) loads the Trusted OS binary to |
| 99 | the beginning of DRAM (0x40000000). |