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git01.mediatek.com / filogic / atf / 2cb874dcf8f29345394c44e0ecc2e300adbb4372 / . / plat / marvell / armada / a3k / common / include / a3700_plat_def.h
blob: 83d95616b9405d0e7a15437f5f66192625eaedc2 [file] [log] [blame]
Konstantin Porotchkine7be6e22018-10-08 16:53:09 +0300[diff] [blame]1/*
Marek Behún5fd234e2021-01-07 21:52:44 +0100[diff] [blame]2 * Copyright (C) 2018-2021 Marvell International Ltd.
Konstantin Porotchkine7be6e22018-10-08 16:53:09 +0300[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]8#ifndef A3700_PLAT_DEF_H
9#define A3700_PLAT_DEF_H
Konstantin Porotchkine7be6e22018-10-08 16:53:09 +0300[diff] [blame]10
11#include <marvell_def.h>
12
13
14#define MVEBU_MAX_CPUS_PER_CLUSTER 2
15
16#define MVEBU_PRIMARY_CPU 0x0
17
18/*
19 * The counter on A3700 is always fed from reference 25M clock (XTAL).
20 * However minimal CPU counter prescaler is 2, so the counter
21 * frequency will be divided by 2, the number is 12.5M
22 */
23#define COUNTER_FREQUENCY 12500000
24
25#define MVEBU_REGS_BASE 0xD0000000
26
27/*****************************************************************************
28 * MVEBU memory map related constants
29 *****************************************************************************
30 */
31/* Aggregate of all devices in the first GB */
32#define DEVICE0_BASE MVEBU_REGS_BASE
33#define DEVICE0_SIZE 0x10000000
34
35/*****************************************************************************
36 * GIC-500 & interrupt handling related constants
37 *****************************************************************************
38 */
39/* Base MVEBU compatible GIC memory map */
40#define MVEBU_GICD_BASE 0x1D00000
41#define MVEBU_GICR_BASE 0x1D40000
42#define MVEBU_GICC_BASE 0x1D80000
43
Marek Behún5fd234e2021-01-07 21:52:44 +0100[diff] [blame]44/*
45 * CCI-400 base address
46 * This address is absolute, not relative to MVEBU_REGS_BASE.
47 * This is not the default CCI base address (that would be 0xD8000000).
48 * Rather we remap CCI to this address to better utilize the address space.
49 * (The remapping is done in plat/marvell/armada/a3k/common/plat_cci.c)
50 */
51#define MVEBU_CCI_BASE 0xFE000000
Konstantin Porotchkine7be6e22018-10-08 16:53:09 +0300[diff] [blame]52
53/*****************************************************************************
54 * North and south bridge register base
55 *****************************************************************************
56 */
57#define MVEBU_NB_REGS_BASE (MVEBU_REGS_BASE + 0x13000)
58#define MVEBU_SB_REGS_BASE (MVEBU_REGS_BASE + 0x18000)
59
60/*****************************************************************************
61 * GPIO registers related constants
62 *****************************************************************************
63 */
64/* North and south bridge GPIO register base address */
65#define MVEBU_NB_GPIO_REG_BASE (MVEBU_NB_REGS_BASE + 0x800)
66#define MVEBU_NB_GPIO_IRQ_REG_BASE (MVEBU_NB_REGS_BASE + 0xC00)
67#define MVEBU_SB_GPIO_REG_BASE (MVEBU_SB_REGS_BASE + 0x800)
68#define MVEBU_SB_GPIO_IRQ_REG_BASE (MVEBU_SB_REGS_BASE + 0xC00)
69#define MVEBU_NB_SB_IRQ_REG_BASE (MVEBU_REGS_BASE + 0x8A00)
70
71/* North Bridge GPIO selection register */
72#define MVEBU_NB_GPIO_SEL_REG (MVEBU_NB_GPIO_REG_BASE + 0x30)
73#define MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG (MVEBU_NB_GPIO_REG_BASE + 0x04)
74/* I2C1 GPIO Enable bit offset */
75#define MVEBU_GPIO_TW1_GPIO_EN_OFF (10)
76/* SPI pins mode bit offset */
77#define MVEBU_GPIO_NB_SPI_PIN_MODE_OFF (28)
78
79/*****************************************************************************
80 * DRAM registers related constants
81 *****************************************************************************
82 */
83#define MVEBU_DRAM_REG_BASE (MVEBU_REGS_BASE)
84
85/*****************************************************************************
86 * SB wake-up registers related constants
87 *****************************************************************************
88 */
89#define MVEBU_SB_WAKEUP_REG_BASE (MVEBU_REGS_BASE + 0x19000)
90
91/*****************************************************************************
92 * PMSU registers related constants
93 *****************************************************************************
94 */
95#define MVEBU_PMSU_REG_BASE (MVEBU_REGS_BASE + 0x14000)
96
97/*****************************************************************************
98 * North Bridge Step-Down Registers
99 *****************************************************************************
100 */
101#define MVEBU_NB_STEP_DOWN_REG_BASE (MVEBU_REGS_BASE + 0x12800)
102
103/*****************************************************************************
104 * DRAM CS memory map register base
105 *****************************************************************************
106 */
107#define MVEBU_CS_MMAP_REG_BASE (MVEBU_REGS_BASE + 0x200)
108
109/*****************************************************************************
110 * CPU decoder window registers related constants
111 *****************************************************************************
112 */
113#define MVEBU_CPU_DEC_WIN_REG_BASE (MVEBU_REGS_BASE + 0xCF00)
114
115/*****************************************************************************
116 * AVS registers related constants
117 *****************************************************************************
118 */
119#define MVEBU_AVS_REG_BASE (MVEBU_REGS_BASE + 0x11500)
120
121
122/*****************************************************************************
123 * AVS registers related constants
124 *****************************************************************************
125 */
126#define MVEBU_COMPHY_REG_BASE (MVEBU_REGS_BASE + 0x18300)
127
Marek Behún19d85782021-01-05 14:01:05 +0100[diff] [blame]128/*****************************************************************************
129 * Cortex-M3 Secure Processor Mailbox constants
130 *****************************************************************************
131 */
132#define MVEBU_RWTM_REG_BASE (MVEBU_REGS_BASE + 0xB0000)
133
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]134#endif /* A3700_PLAT_DEF_H */