Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <bakery_lock.h> |
| 32 | #include <mmio.h> |
| 33 | #include <platform.h> |
| 34 | #include <arch_helpers.h> |
| 35 | #include "pm_ipi.h" |
| 36 | #include "../zynqmp_private.h" |
| 37 | |
| 38 | /* IPI message buffers */ |
| 39 | #define IPI_BUFFER_BASEADDR 0xFF990000U |
| 40 | |
| 41 | #define IPI_BUFFER_RPU_0_BASE (IPI_BUFFER_BASEADDR + 0x0U) |
| 42 | #define IPI_BUFFER_RPU_1_BASE (IPI_BUFFER_BASEADDR + 0x200U) |
| 43 | #define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) |
| 44 | #define IPI_BUFFER_PL_0_BASE (IPI_BUFFER_BASEADDR + 0x600U) |
| 45 | #define IPI_BUFFER_PL_1_BASE (IPI_BUFFER_BASEADDR + 0x800U) |
| 46 | #define IPI_BUFFER_PL_2_BASE (IPI_BUFFER_BASEADDR + 0xA00U) |
| 47 | #define IPI_BUFFER_PL_3_BASE (IPI_BUFFER_BASEADDR + 0xC00U) |
| 48 | #define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U) |
| 49 | |
| 50 | #define IPI_BUFFER_TARGET_RPU_0_OFFSET 0x0U |
| 51 | #define IPI_BUFFER_TARGET_RPU_1_OFFSET 0x40U |
| 52 | #define IPI_BUFFER_TARGET_APU_OFFSET 0x80U |
| 53 | #define IPI_BUFFER_TARGET_PL_0_OFFSET 0xC0U |
| 54 | #define IPI_BUFFER_TARGET_PL_1_OFFSET 0x100U |
| 55 | #define IPI_BUFFER_TARGET_PL_2_OFFSET 0x140U |
| 56 | #define IPI_BUFFER_TARGET_PL_3_OFFSET 0x180U |
| 57 | #define IPI_BUFFER_TARGET_PMU_OFFSET 0x1C0U |
| 58 | |
| 59 | #define IPI_BUFFER_REQ_OFFSET 0x0U |
| 60 | #define IPI_BUFFER_RESP_OFFSET 0x20U |
| 61 | |
| 62 | /* IPI Base Address */ |
| 63 | #define IPI_BASEADDR 0XFF300000 |
| 64 | |
| 65 | /* APU's IPI registers */ |
| 66 | #define IPI_APU_ISR (IPI_BASEADDR + 0X00000010) |
| 67 | #define IPI_APU_IER (IPI_BASEADDR + 0X00000018) |
| 68 | #define IPI_APU_IDR (IPI_BASEADDR + 0X0000001C) |
| 69 | #define IPI_APU_ISR_PMU_0_MASK 0X00010000 |
| 70 | #define IPI_APU_IER_PMU_0_MASK 0X00010000 |
| 71 | |
| 72 | #define IPI_TRIG_OFFSET 0 |
| 73 | #define IPI_OBS_OFFSET 4 |
| 74 | |
| 75 | /* Power Management IPI interrupt number */ |
| 76 | #define PM_INT_NUM 0 |
| 77 | #define IPI_PMU_PM_INT_BASE (IPI_PMU_0_TRIG + (PM_INT_NUM * 0x1000)) |
| 78 | #define IPI_PMU_PM_INT_MASK (IPI_APU_ISR_PMU_0_MASK << PM_INT_NUM) |
| 79 | #if (PM_INT_NUM < 0 || PM_INT_NUM > 3) |
| 80 | #error PM_INT_NUM value out of range |
| 81 | #endif |
| 82 | |
| 83 | #define IPI_APU_MASK 1U |
| 84 | |
| 85 | static bakery_lock_t pm_secure_lock; |
| 86 | |
| 87 | const struct pm_ipi apu_ipi = { |
| 88 | .mask = IPI_APU_MASK, |
| 89 | .base = IPI_BASEADDR, |
| 90 | .buffer_base = IPI_BUFFER_APU_BASE, |
| 91 | }; |
| 92 | |
| 93 | /** |
| 94 | * pm_ipi_init() - Initialize IPI peripheral for communication with PMU |
| 95 | * |
| 96 | * @return On success, the initialization function must return 0. |
| 97 | * Any other return value will cause the framework to ignore |
| 98 | * the service |
| 99 | * |
| 100 | * Enable interrupts at registered entrance in IPI peripheral |
| 101 | * Called from pm_setup initialization function |
| 102 | */ |
| 103 | int pm_ipi_init(void) |
| 104 | { |
| 105 | bakery_lock_init(&pm_secure_lock); |
| 106 | |
| 107 | /* IPI Interrupts Clear & Disable */ |
| 108 | mmio_write_32(IPI_APU_ISR, 0xffffffff); |
| 109 | mmio_write_32(IPI_APU_IDR, 0xffffffff); |
| 110 | |
| 111 | return 0; |
| 112 | } |
| 113 | |
| 114 | /** |
| 115 | * pm_ipi_wait() - wait for pmu to handle request |
| 116 | * @proc proc which is waiting for PMU to handle request |
| 117 | */ |
| 118 | static enum pm_ret_status pm_ipi_wait(const struct pm_proc *proc) |
| 119 | { |
| 120 | int status; |
| 121 | |
| 122 | /* Wait until previous interrupt is handled by PMU */ |
| 123 | do { |
| 124 | status = mmio_read_32(proc->ipi->base + IPI_OBS_OFFSET) & |
| 125 | IPI_PMU_PM_INT_MASK; |
| 126 | /* TODO: 1) Use timer to add delay between read attempts */ |
| 127 | /* TODO: 2) Return PM_RET_ERR_TIMEOUT if this times out */ |
| 128 | } while (status); |
| 129 | |
| 130 | return PM_RET_SUCCESS; |
| 131 | } |
| 132 | |
| 133 | /** |
| 134 | * pm_ipi_send_common() - Sends IPI request to the PMU |
| 135 | * @proc Pointer to the processor who is initiating request |
| 136 | * @payload API id and call arguments to be written in IPI buffer |
| 137 | * |
| 138 | * Send an IPI request to the power controller. Caller needs to hold |
| 139 | * the 'pm_secure_lock' lock. |
| 140 | * |
| 141 | * @return Returns status, either success or error+reason |
| 142 | */ |
| 143 | static enum pm_ret_status pm_ipi_send_common(const struct pm_proc *proc, |
| 144 | uint32_t payload[PAYLOAD_ARG_CNT]) |
| 145 | { |
| 146 | unsigned int offset = 0; |
| 147 | uintptr_t buffer_base = proc->ipi->buffer_base + |
| 148 | IPI_BUFFER_TARGET_PMU_OFFSET + |
| 149 | IPI_BUFFER_REQ_OFFSET; |
| 150 | |
| 151 | /* Wait until previous interrupt is handled by PMU */ |
| 152 | pm_ipi_wait(proc); |
| 153 | |
| 154 | /* Write payload into IPI buffer */ |
| 155 | for (size_t i = 0; i < PAYLOAD_ARG_CNT; i++) { |
| 156 | mmio_write_32(buffer_base + offset, payload[i]); |
| 157 | offset += PAYLOAD_ARG_SIZE; |
| 158 | } |
| 159 | /* Generate IPI to PMU */ |
| 160 | mmio_write_32(proc->ipi->base + IPI_TRIG_OFFSET, IPI_PMU_PM_INT_MASK); |
| 161 | |
| 162 | return PM_RET_SUCCESS; |
| 163 | } |
| 164 | |
| 165 | /** |
| 166 | * pm_ipi_send() - Sends IPI request to the PMU |
| 167 | * @proc Pointer to the processor who is initiating request |
| 168 | * @payload API id and call arguments to be written in IPI buffer |
| 169 | * |
| 170 | * Send an IPI request to the power controller. |
| 171 | * |
| 172 | * @return Returns status, either success or error+reason |
| 173 | */ |
| 174 | enum pm_ret_status pm_ipi_send(const struct pm_proc *proc, |
| 175 | uint32_t payload[PAYLOAD_ARG_CNT]) |
| 176 | { |
| 177 | enum pm_ret_status ret; |
| 178 | |
| 179 | bakery_lock_get(&pm_secure_lock); |
| 180 | |
| 181 | ret = pm_ipi_send_common(proc, payload); |
| 182 | |
| 183 | bakery_lock_release(&pm_secure_lock); |
| 184 | |
| 185 | return ret; |
| 186 | } |
| 187 | |
| 188 | |
| 189 | /** |
| 190 | * pm_ipi_buff_read() - Reads IPI response after PMU has handled interrupt |
| 191 | * @proc Pointer to the processor who is waiting and reading response |
| 192 | * @value Used to return value from 2nd IPI buffer element (optional) |
| 193 | * |
| 194 | * @return Returns status, either success or error+reason |
| 195 | */ |
| 196 | static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc, |
| 197 | unsigned int *value) |
| 198 | { |
| 199 | uintptr_t buffer_base = proc->ipi->buffer_base + |
| 200 | IPI_BUFFER_TARGET_PMU_OFFSET + |
| 201 | IPI_BUFFER_RESP_OFFSET; |
| 202 | |
| 203 | pm_ipi_wait(proc); |
| 204 | |
| 205 | /* |
| 206 | * Read response from IPI buffer |
| 207 | * buf-0: success or error+reason |
| 208 | * buf-1: value |
| 209 | * buf-2: unused |
| 210 | * buf-3: unused |
| 211 | */ |
| 212 | if (value != NULL) |
| 213 | *value = mmio_read_32(buffer_base + PAYLOAD_ARG_SIZE); |
| 214 | |
| 215 | return mmio_read_32(buffer_base); |
| 216 | } |
| 217 | |
| 218 | /** |
| 219 | * pm_ipi_send_sync() - Sends IPI request to the PMU |
| 220 | * @proc Pointer to the processor who is initiating request |
| 221 | * @payload API id and call arguments to be written in IPI buffer |
| 222 | * @value Used to return value from 2nd IPI buffer element (optional) |
| 223 | * |
| 224 | * Send an IPI request to the power controller and wait for it to be handled. |
| 225 | * |
| 226 | * @return Returns status, either success or error+reason and, optionally, |
| 227 | * @value |
| 228 | */ |
| 229 | enum pm_ret_status pm_ipi_send_sync(const struct pm_proc *proc, |
| 230 | uint32_t payload[PAYLOAD_ARG_CNT], |
| 231 | unsigned int *value) |
| 232 | { |
| 233 | enum pm_ret_status ret; |
| 234 | |
| 235 | bakery_lock_get(&pm_secure_lock); |
| 236 | |
| 237 | ret = pm_ipi_send_common(proc, payload); |
| 238 | if (ret != PM_RET_SUCCESS) |
| 239 | goto unlock; |
| 240 | |
| 241 | ret = pm_ipi_buff_read(proc, value); |
| 242 | |
| 243 | unlock: |
| 244 | bakery_lock_release(&pm_secure_lock); |
| 245 | |
| 246 | return ret; |
| 247 | } |