Jiafei Pan | b9d543c | 2022-02-18 15:26:08 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2022 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOC_H |
| 8 | #define SOC_H |
| 9 | |
| 10 | /* Chassis specific defines - common across SoC's of a particular platform */ |
| 11 | #include "dcfg_lsch3.h" |
| 12 | #include "soc_default_base_addr.h" |
| 13 | #include "soc_default_helper_macros.h" |
| 14 | |
| 15 | /* |
| 16 | * SVR Definition of LS1088A |
| 17 | * A: without security |
| 18 | * AE: with security |
| 19 | * (not include major and minor rev) |
| 20 | */ |
| 21 | #define SVR_LS1044A 0x870323 |
| 22 | #define SVR_LS1044AE 0x870322 |
| 23 | #define SVR_LS1048A 0x870321 |
| 24 | #define SVR_LS1048AE 0x870320 |
| 25 | #define SVR_LS1084A 0x870303 |
| 26 | #define SVR_LS1084AE 0x870302 |
| 27 | #define SVR_LS1088A 0x870301 |
| 28 | #define SVR_LS1088AE 0x870300 |
| 29 | |
| 30 | #define SVR_WO_E 0xFFFFFE |
| 31 | |
| 32 | /* Number of cores in platform */ |
| 33 | #define NUMBER_OF_CLUSTERS 2 |
| 34 | #define CORES_PER_CLUSTER 4 |
| 35 | #define PLATFORM_CORE_COUNT (NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER) |
| 36 | |
| 37 | /* set to 0 if the clusters are not symmetrical */ |
| 38 | #define SYMMETRICAL_CLUSTERS 1 |
| 39 | |
| 40 | |
| 41 | #define NUM_DRAM_REGIONS 2 |
| 42 | #define NXP_DRAM0_ADDR 0x80000000 |
| 43 | #define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */ |
| 44 | |
| 45 | #define NXP_DRAM1_ADDR 0x8080000000 |
| 46 | #define NXP_DRAM1_MAX_SIZE 0x7F80000000 /* 510 G */ |
| 47 | |
| 48 | /* DRAM0 Size defined in platform_def.h */ |
| 49 | #define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE |
| 50 | |
| 51 | #define NXP_POWMGTDCR 0x700123C20 |
| 52 | |
| 53 | /* epu register offsets and values */ |
| 54 | #define EPU_EPGCR_OFFSET 0x0 |
| 55 | #define EPU_EPIMCR10_OFFSET 0x128 |
| 56 | #define EPU_EPCTR10_OFFSET 0xa28 |
| 57 | #define EPU_EPCCR10_OFFSET 0x828 |
| 58 | |
| 59 | #ifdef EPU_EPCCR10_VAL |
| 60 | #undef EPU_EPCCR10_VAL |
| 61 | #endif |
| 62 | #define EPU_EPCCR10_VAL 0xf2800000 |
| 63 | |
| 64 | #define EPU_EPIMCR10_VAL 0xba000000 |
| 65 | #define EPU_EPCTR10_VAL 0x0 |
| 66 | #define EPU_EPGCR_VAL (1 << 31) |
| 67 | |
| 68 | /* pmu register offsets and values */ |
| 69 | #define PMU_PCPW20SR_OFFSET 0x830 |
| 70 | #define PMU_CLAINACTSETR_OFFSET 0x1100 |
| 71 | #define PMU_CLAINACTCLRR_OFFSET 0x1104 |
| 72 | #define PMU_CLSINACTSETR_OFFSET 0x1108 |
| 73 | #define PMU_CLSINACTCLRR_OFFSET 0x110C |
| 74 | #define PMU_CLL2FLUSHSETR_OFFSET 0x1110 |
| 75 | #define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114 |
| 76 | #define PMU_CLL2FLUSHSR_OFFSET 0x1118 |
| 77 | #define PMU_POWMGTCSR_OFFSET 0x4000 |
| 78 | #define PMU_IPPDEXPCR0_OFFSET 0x4040 |
| 79 | #define PMU_IPPDEXPCR1_OFFSET 0x4044 |
| 80 | #define PMU_IPPDEXPCR2_OFFSET 0x4048 |
| 81 | #define PMU_IPPDEXPCR3_OFFSET 0x404C |
| 82 | #define PMU_IPPDEXPCR4_OFFSET 0x4050 |
| 83 | #define PMU_IPPDEXPCR5_OFFSET 0x4054 |
| 84 | #define PMU_IPSTPCR0_OFFSET 0x4120 |
| 85 | #define PMU_IPSTPCR1_OFFSET 0x4124 |
| 86 | #define PMU_IPSTPCR2_OFFSET 0x4128 |
| 87 | #define PMU_IPSTPCR3_OFFSET 0x412C |
| 88 | #define PMU_IPSTPCR4_OFFSET 0x4130 |
| 89 | #define PMU_IPSTPCR5_OFFSET 0x4134 |
| 90 | #define PMU_IPSTPCR6_OFFSET 0x4138 |
| 91 | #define PMU_IPSTPACK0_OFFSET 0x4140 |
| 92 | #define PMU_IPSTPACK1_OFFSET 0x4144 |
| 93 | #define PMU_IPSTPACK2_OFFSET 0x4148 |
| 94 | #define PMU_IPSTPACK3_OFFSET 0x414C |
| 95 | #define PMU_IPSTPACK4_OFFSET 0x4150 |
| 96 | #define PMU_IPSTPACK5_OFFSET 0x4154 |
| 97 | #define PMU_IPSTPACK6_OFFSET 0x4158 |
| 98 | #define PMU_POWMGTCSR_VAL (1 << 20) |
| 99 | |
| 100 | #define IPPDEXPCR0_MASK 0xFFFFFFFF |
| 101 | #define IPPDEXPCR1_MASK 0xFFFFFFFF |
| 102 | #define IPPDEXPCR2_MASK 0xFFFFFFFF |
| 103 | #define IPPDEXPCR3_MASK 0xFFFFFFFF |
| 104 | #define IPPDEXPCR4_MASK 0xFFFFFFFF |
| 105 | #define IPPDEXPCR5_MASK 0xFFFFFFFF |
| 106 | |
| 107 | /* DEVDISR5_FLX_TMR */ |
| 108 | #define IPPDEXPCR_FLX_TMR 0x00004000 |
| 109 | #define DEVDISR5_FLX_TMR 0x00004000 |
| 110 | |
| 111 | #define IPSTPCR0_VALUE 0x0041310C |
| 112 | #define IPSTPCR1_VALUE 0x000003FF |
| 113 | #define IPSTPCR2_VALUE 0x00013006 |
| 114 | |
Elyes Haouas | 2be03c0 | 2023-02-13 09:14:48 +0100 | [diff] [blame^] | 115 | /* Don't stop UART */ |
Jiafei Pan | b9d543c | 2022-02-18 15:26:08 +0800 | [diff] [blame] | 116 | #define IPSTPCR3_VALUE 0x0000033A |
| 117 | |
| 118 | #define IPSTPCR4_VALUE 0x00103300 |
| 119 | #define IPSTPCR5_VALUE 0x00000001 |
| 120 | #define IPSTPCR6_VALUE 0x00000000 |
| 121 | |
| 122 | |
| 123 | #define TZPC_BLOCK_SIZE 0x1000 |
| 124 | |
| 125 | /* PORSR1 */ |
| 126 | #define PORSR1_RCW_MASK 0xFF800000 |
| 127 | #define PORSR1_RCW_SHIFT 23 |
| 128 | |
| 129 | /* CFG_RCW_SRC[6:0] */ |
| 130 | #define RCW_SRC_TYPE_MASK 0x70 |
| 131 | |
| 132 | /* RCW SRC NOR */ |
| 133 | #define NOR_16B_VAL 0x20 |
| 134 | |
| 135 | /* |
| 136 | * RCW SRC Serial Flash |
| 137 | * 1. SERAIL NOR (QSPI) |
| 138 | * 2. OTHERS (SD/MMC, SPI, I2C1) |
| 139 | */ |
| 140 | #define RCW_SRC_SERIAL_MASK 0x7F |
| 141 | #define QSPI_VAL 0x62 |
| 142 | #define SDHC_VAL 0x40 |
| 143 | #define EMMC_VAL 0x41 |
| 144 | |
| 145 | /* |
| 146 | * Required LS standard platform porting definitions |
| 147 | * for CCN-504 - Read from RN-F node ID register |
| 148 | */ |
| 149 | #define PLAT_CLUSTER_TO_CCN_ID_MAP 1, 9, 11, 19 |
| 150 | |
| 151 | /* Defines required for using XLAT tables from ARM common code */ |
| 152 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) |
| 153 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) |
| 154 | |
| 155 | /* |
| 156 | * Clock Divisors |
| 157 | */ |
| 158 | #define NXP_PLATFORM_CLK_DIVIDER 1 |
| 159 | #define NXP_UART_CLK_DIVIDER 2 |
| 160 | |
| 161 | /* dcfg register offsets and values */ |
| 162 | #define DCFG_DEVDISR1_OFFSET 0x70 |
| 163 | #define DCFG_DEVDISR2_OFFSET 0x74 |
| 164 | #define DCFG_DEVDISR3_OFFSET 0x78 |
| 165 | #define DCFG_DEVDISR5_OFFSET 0x80 |
| 166 | #define DCFG_DEVDISR6_OFFSET 0x84 |
| 167 | |
| 168 | #define DCFG_DEVDISR1_SEC (1 << 22) |
| 169 | #define DCFG_DEVDISR3_QBMAIN (1 << 12) |
| 170 | #define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5) |
| 171 | #define DCFG_DEVDISR5_MEM (1 << 0) |
| 172 | |
| 173 | #define DEVDISR1_VALUE 0x0041310c |
| 174 | #define DEVDISR2_VALUE 0x000003ff |
| 175 | #define DEVDISR3_VALUE 0x00013006 |
| 176 | #define DEVDISR4_VALUE 0x0000033e |
| 177 | #define DEVDISR5_VALUE 0x00103300 |
| 178 | #define DEVDISR6_VALUE 0x00000001 |
| 179 | |
| 180 | /* |
| 181 | * pwr mgmt features supported in the soc-specific code: |
| 182 | * value == 0x0, the soc code does not support this feature |
| 183 | * value != 0x0, the soc code supports this feature |
| 184 | */ |
| 185 | #define SOC_CORE_RELEASE 0x1 |
| 186 | #define SOC_CORE_RESTART 0x1 |
| 187 | #define SOC_CORE_OFF 0x1 |
| 188 | #define SOC_CORE_STANDBY 0x1 |
| 189 | #define SOC_CORE_PWR_DWN 0x1 |
| 190 | #define SOC_CLUSTER_STANDBY 0x1 |
| 191 | #define SOC_CLUSTER_PWR_DWN 0x1 |
| 192 | #define SOC_SYSTEM_STANDBY 0x1 |
| 193 | #define SOC_SYSTEM_PWR_DWN 0x1 |
| 194 | #define SOC_SYSTEM_OFF 0x1 |
| 195 | #define SOC_SYSTEM_RESET 0x1 |
| 196 | |
| 197 | #define SYSTEM_PWR_DOMAINS 1 |
| 198 | #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ |
| 199 | NUMBER_OF_CLUSTERS + \ |
| 200 | SYSTEM_PWR_DOMAINS) |
| 201 | |
| 202 | /* Power state coordination occurs at the system level */ |
| 203 | #define PLAT_PD_COORD_LVL MPIDR_AFFLVL2 |
| 204 | #define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL |
| 205 | |
| 206 | /* Local power state for power domains in Run state */ |
| 207 | #define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN |
| 208 | |
| 209 | /* define retention state */ |
| 210 | #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) |
| 211 | #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE |
| 212 | |
| 213 | /* define power-down state */ |
| 214 | #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) |
| 215 | #define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE |
| 216 | |
| 217 | #ifndef __ASSEMBLER__ |
| 218 | /* CCI slave interfaces */ |
| 219 | static const int cci_map[] = { |
| 220 | 3, |
| 221 | 4, |
| 222 | }; |
| 223 | void soc_init_lowlevel(void); |
| 224 | void soc_init_percpu(void); |
| 225 | void _soc_set_start_addr(unsigned long addr); |
| 226 | void _set_platform_security(void); |
| 227 | #endif |
| 228 | |
| 229 | #endif /* SOC_H */ |