Jacky Bai | 07ed02c | 2020-06-03 14:28:45 +0800 | [diff] [blame] | 1 | /* |
Jacky Bai | 135ece1 | 2022-03-31 10:26:33 +0800 | [diff] [blame] | 2 | * Copyright 2019-2022 NXP |
Jacky Bai | 07ed02c | 2020-06-03 14:28:45 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdbool.h> |
| 8 | #include <stdint.h> |
| 9 | #include <stdlib.h> |
| 10 | |
| 11 | #include <common/debug.h> |
| 12 | #include <drivers/delay_timer.h> |
| 13 | #include <lib/mmio.h> |
| 14 | #include <lib/psci/psci.h> |
| 15 | #include <lib/smccc.h> |
| 16 | #include <services/std_svc.h> |
| 17 | |
| 18 | #include <gpc.h> |
| 19 | #include <imx_aipstz.h> |
| 20 | #include <imx_sip_svc.h> |
| 21 | #include <platform_def.h> |
| 22 | |
| 23 | #define CCGR(x) (0x4000 + (x) * 0x10) |
| 24 | #define IMR_NUM U(5) |
| 25 | |
| 26 | struct imx_noc_setting { |
| 27 | uint32_t domain_id; |
| 28 | uint32_t start; |
| 29 | uint32_t end; |
| 30 | uint32_t prioriy; |
| 31 | uint32_t mode; |
| 32 | uint32_t socket_qos_en; |
| 33 | }; |
| 34 | |
| 35 | enum clk_type { |
| 36 | CCM_ROOT_SLICE, |
| 37 | CCM_CCGR, |
| 38 | }; |
| 39 | |
| 40 | struct clk_setting { |
| 41 | uint32_t offset; |
| 42 | uint32_t val; |
| 43 | enum clk_type type; |
| 44 | }; |
| 45 | |
| 46 | enum pu_domain_id { |
| 47 | /* hsio ss */ |
| 48 | HSIOMIX, |
| 49 | PCIE_PHY, |
| 50 | USB1_PHY, |
| 51 | USB2_PHY, |
| 52 | MLMIX, |
| 53 | AUDIOMIX, |
| 54 | /* gpu ss */ |
| 55 | GPUMIX, |
| 56 | GPU2D, |
| 57 | GPU3D, |
| 58 | /* vpu ss */ |
| 59 | VPUMIX, |
| 60 | VPU_G1, |
| 61 | VPU_G2, |
| 62 | VPU_H1, |
| 63 | /* media ss */ |
| 64 | MEDIAMIX, |
| 65 | MEDIAMIX_ISPDWP, |
| 66 | MIPI_PHY1, |
| 67 | MIPI_PHY2, |
| 68 | /* HDMI ss */ |
| 69 | HDMIMIX, |
| 70 | HDMI_PHY, |
| 71 | DDRMIX, |
Jacky Bai | 135ece1 | 2022-03-31 10:26:33 +0800 | [diff] [blame] | 72 | MAX_DOMAINS, |
Jacky Bai | 07ed02c | 2020-06-03 14:28:45 +0800 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | /* PU domain, add some hole to minimize the uboot change */ |
Jacky Bai | 135ece1 | 2022-03-31 10:26:33 +0800 | [diff] [blame] | 76 | static struct imx_pwr_domain pu_domains[MAX_DOMAINS] = { |
Jacky Bai | 07ed02c | 2020-06-03 14:28:45 +0800 | [diff] [blame] | 77 | [MIPI_PHY1] = IMX_PD_DOMAIN(MIPI_PHY1, false), |
| 78 | [PCIE_PHY] = IMX_PD_DOMAIN(PCIE_PHY, false), |
| 79 | [USB1_PHY] = IMX_PD_DOMAIN(USB1_PHY, true), |
| 80 | [USB2_PHY] = IMX_PD_DOMAIN(USB2_PHY, true), |
| 81 | [MLMIX] = IMX_MIX_DOMAIN(MLMIX, false), |
| 82 | [AUDIOMIX] = IMX_MIX_DOMAIN(AUDIOMIX, false), |
| 83 | [GPU2D] = IMX_PD_DOMAIN(GPU2D, false), |
| 84 | [GPUMIX] = IMX_MIX_DOMAIN(GPUMIX, false), |
| 85 | [VPUMIX] = IMX_MIX_DOMAIN(VPUMIX, false), |
| 86 | [GPU3D] = IMX_PD_DOMAIN(GPU3D, false), |
| 87 | [MEDIAMIX] = IMX_MIX_DOMAIN(MEDIAMIX, false), |
| 88 | [VPU_G1] = IMX_PD_DOMAIN(VPU_G1, false), |
| 89 | [VPU_G2] = IMX_PD_DOMAIN(VPU_G2, false), |
| 90 | [VPU_H1] = IMX_PD_DOMAIN(VPU_H1, false), |
| 91 | [HDMIMIX] = IMX_MIX_DOMAIN(HDMIMIX, false), |
| 92 | [HDMI_PHY] = IMX_PD_DOMAIN(HDMI_PHY, false), |
| 93 | [MIPI_PHY2] = IMX_PD_DOMAIN(MIPI_PHY2, false), |
| 94 | [HSIOMIX] = IMX_MIX_DOMAIN(HSIOMIX, false), |
| 95 | [MEDIAMIX_ISPDWP] = IMX_PD_DOMAIN(MEDIAMIX_ISPDWP, false), |
| 96 | }; |
| 97 | |
| 98 | static struct imx_noc_setting noc_setting[] = { |
| 99 | {MLMIX, 0x180, 0x180, 0x80000303, 0x0, 0x0}, |
| 100 | {AUDIOMIX, 0x200, 0x200, 0x80000303, 0x0, 0x0}, |
| 101 | {AUDIOMIX, 0x280, 0x480, 0x80000404, 0x0, 0x0}, |
| 102 | {GPUMIX, 0x500, 0x580, 0x80000303, 0x0, 0x0}, |
| 103 | {HDMIMIX, 0x600, 0x680, 0x80000202, 0x0, 0x1}, |
| 104 | {HDMIMIX, 0x700, 0x700, 0x80000505, 0x0, 0x0}, |
| 105 | {HSIOMIX, 0x780, 0x900, 0x80000303, 0x0, 0x0}, |
| 106 | {MEDIAMIX, 0x980, 0xb80, 0x80000202, 0x0, 0x1}, |
| 107 | {MEDIAMIX_ISPDWP, 0xc00, 0xd00, 0x80000505, 0x0, 0x0}, |
| 108 | {VPU_G1, 0xd80, 0xd80, 0x80000303, 0x0, 0x0}, |
| 109 | {VPU_G2, 0xe00, 0xe00, 0x80000303, 0x0, 0x0}, |
| 110 | {VPU_H1, 0xe80, 0xe80, 0x80000303, 0x0, 0x0} |
| 111 | }; |
| 112 | |
| 113 | static struct clk_setting hsiomix_clk[] = { |
| 114 | { 0x8380, 0x0, CCM_ROOT_SLICE }, |
| 115 | { 0x44d0, 0x0, CCM_CCGR }, |
| 116 | { 0x45c0, 0x0, CCM_CCGR }, |
| 117 | }; |
| 118 | |
| 119 | static struct aipstz_cfg aipstz5[] = { |
| 120 | {IMX_AIPSTZ5, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, }, |
| 121 | {0}, |
| 122 | }; |
| 123 | |
| 124 | static unsigned int pu_domain_status; |
| 125 | |
| 126 | static void imx_noc_qos(unsigned int domain_id) |
| 127 | { |
| 128 | unsigned int i; |
| 129 | uint32_t hurry; |
| 130 | |
| 131 | if (domain_id == HDMIMIX) { |
| 132 | mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22018); |
| 133 | mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL1, 0x22010); |
| 134 | |
| 135 | /* set GPR to make lcdif read hurry level 0x7 */ |
| 136 | hurry = mmio_read_32(IMX_HDMI_CTL_BASE + TX_CONTROL0); |
| 137 | hurry |= 0x00077000; |
| 138 | mmio_write_32(IMX_HDMI_CTL_BASE + TX_CONTROL0, hurry); |
| 139 | } |
| 140 | |
| 141 | if (domain_id == MEDIAMIX) { |
| 142 | /* handle mediamix special */ |
| 143 | mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RSTn_CSR, 0x1FFFFFF); |
| 144 | mmio_write_32(IMX_MEDIAMIX_CTL_BASE + CLK_EN_CSR, 0x1FFFFFF); |
| 145 | mmio_write_32(IMX_MEDIAMIX_CTL_BASE + RST_DIV, 0x40030000); |
| 146 | |
| 147 | /* set GPR to make lcdif read hurry level 0x7 */ |
| 148 | hurry = mmio_read_32(IMX_MEDIAMIX_CTL_BASE + LCDIF_ARCACHE_CTRL); |
| 149 | hurry |= 0xfc00; |
| 150 | mmio_write_32(IMX_MEDIAMIX_CTL_BASE + LCDIF_ARCACHE_CTRL, hurry); |
| 151 | /* set GPR to make isi write hurry level 0x7 */ |
| 152 | hurry = mmio_read_32(IMX_MEDIAMIX_CTL_BASE + ISI_CACHE_CTRL); |
| 153 | hurry |= 0x1ff00000; |
| 154 | mmio_write_32(IMX_MEDIAMIX_CTL_BASE + ISI_CACHE_CTRL, hurry); |
| 155 | } |
| 156 | |
| 157 | /* set MIX NoC */ |
| 158 | for (i = 0; i < ARRAY_SIZE(noc_setting); i++) { |
| 159 | if (noc_setting[i].domain_id == domain_id) { |
| 160 | udelay(50); |
| 161 | uint32_t offset = noc_setting[i].start; |
| 162 | |
| 163 | while (offset <= noc_setting[i].end) { |
| 164 | mmio_write_32(IMX_NOC_BASE + offset + 0x8, noc_setting[i].prioriy); |
| 165 | mmio_write_32(IMX_NOC_BASE + offset + 0xc, noc_setting[i].mode); |
| 166 | mmio_write_32(IMX_NOC_BASE + offset + 0x18, noc_setting[i].socket_qos_en); |
| 167 | offset += 0x80; |
| 168 | } |
| 169 | } |
| 170 | } |
| 171 | } |
| 172 | |
Jacky Bai | 31f0232 | 2019-12-11 16:26:59 +0800 | [diff] [blame] | 173 | void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on) |
Jacky Bai | 07ed02c | 2020-06-03 14:28:45 +0800 | [diff] [blame] | 174 | { |
| 175 | struct imx_pwr_domain *pwr_domain = &pu_domains[domain_id]; |
| 176 | unsigned int i; |
| 177 | |
Jacky Bai | 135ece1 | 2022-03-31 10:26:33 +0800 | [diff] [blame] | 178 | /* validate the domain id */ |
| 179 | if (domain_id >= MAX_DOMAINS) { |
| 180 | return; |
| 181 | } |
| 182 | |
Jacky Bai | 07ed02c | 2020-06-03 14:28:45 +0800 | [diff] [blame] | 183 | if (domain_id == HSIOMIX) { |
| 184 | for (i = 0; i < ARRAY_SIZE(hsiomix_clk); i++) { |
| 185 | hsiomix_clk[i].val = mmio_read_32(IMX_CCM_BASE + hsiomix_clk[i].offset); |
| 186 | mmio_setbits_32(IMX_CCM_BASE + hsiomix_clk[i].offset, |
| 187 | hsiomix_clk[i].type == CCM_ROOT_SLICE ? BIT(28) : 0x3); |
| 188 | } |
| 189 | } |
| 190 | |
| 191 | if (on) { |
| 192 | if (pwr_domain->need_sync) { |
| 193 | pu_domain_status |= (1 << domain_id); |
| 194 | } |
| 195 | |
| 196 | if (domain_id == HDMIMIX) { |
| 197 | /* assert the reset */ |
| 198 | mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0x0); |
| 199 | /* enable all th function clock */ |
| 200 | mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF); |
| 201 | mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x7ffff87e); |
| 202 | } |
| 203 | |
| 204 | /* clear the PGC bit */ |
| 205 | mmio_clrbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); |
| 206 | |
| 207 | /* power up the domain */ |
| 208 | mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, pwr_domain->pwr_req); |
| 209 | |
| 210 | /* wait for power request done */ |
| 211 | while (mmio_read_32(IMX_GPC_BASE + PU_PGC_UP_TRG) & pwr_domain->pwr_req) |
| 212 | ; |
| 213 | |
| 214 | if (domain_id == HDMIMIX) { |
| 215 | /* wait for memory repair done for HDMIMIX */ |
| 216 | while (!(mmio_read_32(IMX_SRC_BASE + 0x94) & BIT(8))) |
| 217 | ; |
| 218 | /* disable all the function clock */ |
| 219 | mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0x0); |
| 220 | mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x0); |
| 221 | /* deassert the reset */ |
| 222 | mmio_write_32(IMX_HDMI_CTL_BASE + RTX_RESET_CTL0, 0xffffffff); |
| 223 | /* enable all the clock again */ |
| 224 | mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF); |
| 225 | mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL1, 0x7ffff87e); |
| 226 | } |
| 227 | |
| 228 | if (domain_id == HSIOMIX) { |
| 229 | /* enable HSIOMIX clock */ |
| 230 | mmio_write_32(IMX_HSIOMIX_CTL_BASE, 0x2); |
| 231 | } |
| 232 | |
| 233 | /* handle the ADB400 sync */ |
| 234 | if (pwr_domain->need_sync) { |
| 235 | /* clear adb power down request */ |
| 236 | mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); |
| 237 | |
| 238 | /* wait for adb power request ack */ |
| 239 | while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) |
| 240 | ; |
| 241 | } |
| 242 | |
| 243 | imx_noc_qos(domain_id); |
| 244 | |
| 245 | /* AIPS5 config is lost when audiomix is off, so need to re-init it */ |
| 246 | if (domain_id == AUDIOMIX) { |
| 247 | imx_aipstz_init(aipstz5); |
| 248 | } |
| 249 | } else { |
| 250 | if (pwr_domain->always_on) { |
| 251 | return; |
| 252 | } |
| 253 | |
| 254 | if (pwr_domain->need_sync) { |
| 255 | pu_domain_status &= ~(1 << domain_id); |
| 256 | } |
| 257 | |
| 258 | /* handle the ADB400 sync */ |
| 259 | if (pwr_domain->need_sync) { |
| 260 | /* set adb power down request */ |
| 261 | mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); |
| 262 | |
| 263 | /* wait for adb power request ack */ |
| 264 | while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) |
| 265 | ; |
| 266 | } |
| 267 | |
| 268 | /* set the PGC bit */ |
| 269 | mmio_setbits_32(IMX_GPC_BASE + pwr_domain->pgc_offset, 0x1); |
| 270 | |
| 271 | /* |
| 272 | * leave the G1, G2, H1 power domain on until VPUMIX power off, |
| 273 | * otherwise system will hang due to VPUMIX ACK |
| 274 | */ |
| 275 | if (domain_id == VPU_H1 || domain_id == VPU_G1 || domain_id == VPU_G2) { |
| 276 | return; |
| 277 | } |
| 278 | |
| 279 | if (domain_id == VPUMIX) { |
| 280 | mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ | |
| 281 | VPU_G2_PWR_REQ | VPU_H1_PWR_REQ); |
| 282 | |
| 283 | while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ | |
| 284 | VPU_G2_PWR_REQ | VPU_H1_PWR_REQ)) |
| 285 | ; |
| 286 | } |
| 287 | |
| 288 | /* power down the domain */ |
| 289 | mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); |
| 290 | |
| 291 | /* wait for power request done */ |
| 292 | while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) |
| 293 | ; |
| 294 | |
| 295 | if (domain_id == HDMIMIX) { |
| 296 | /* disable all the clocks of HDMIMIX */ |
| 297 | mmio_write_32(IMX_HDMI_CTL_BASE + 0x40, 0x0); |
| 298 | mmio_write_32(IMX_HDMI_CTL_BASE + 0x50, 0x0); |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | if (domain_id == HSIOMIX) { |
| 303 | for (i = 0; i < ARRAY_SIZE(hsiomix_clk); i++) { |
| 304 | mmio_write_32(IMX_CCM_BASE + hsiomix_clk[i].offset, hsiomix_clk[i].val); |
| 305 | } |
| 306 | } |
| 307 | } |
| 308 | |
| 309 | void imx_gpc_init(void) |
| 310 | { |
| 311 | uint32_t val; |
| 312 | unsigned int i; |
| 313 | |
| 314 | /* mask all the wakeup irq by default */ |
| 315 | for (i = 0; i < IMR_NUM; i++) { |
| 316 | mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0); |
| 317 | mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0); |
| 318 | mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0); |
| 319 | mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0); |
| 320 | mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0); |
| 321 | } |
| 322 | |
| 323 | val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); |
| 324 | /* use GIC wake_request to wakeup C0~C3 from LPM */ |
| 325 | val |= CORE_WKUP_FROM_GIC; |
| 326 | /* clear the MASTER0 LPM handshake */ |
| 327 | val &= ~MASTER0_LPM_HSK; |
| 328 | mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); |
| 329 | |
| 330 | /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */ |
| 331 | mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING | |
| 332 | MASTER2_MAPPING)); |
| 333 | |
| 334 | /* set all mix/PU in A53 domain */ |
| 335 | mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0x3fffff); |
| 336 | |
| 337 | /* |
| 338 | * Set the CORE & SCU power up timing: |
| 339 | * SW = 0x1, SW2ISO = 0x1; |
Elyes Haouas | 2be03c0 | 2023-02-13 09:14:48 +0100 | [diff] [blame^] | 340 | * the CPU CORE and SCU power up timing counter |
Jacky Bai | 07ed02c | 2020-06-03 14:28:45 +0800 | [diff] [blame] | 341 | * is drived by 32K OSC, each domain's power up |
| 342 | * latency is (SW + SW2ISO) / 32768 |
| 343 | */ |
| 344 | mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x401); |
| 345 | mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x401); |
| 346 | mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x401); |
| 347 | mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x401); |
| 348 | mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x401); |
| 349 | mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING, |
| 350 | (0x59 << TMC_TMR_SHIFT) | 0x5B | (0x2 << TRC1_TMC_SHIFT)); |
| 351 | |
| 352 | /* set DUMMY PDN/PUP ACK by default for A53 domain */ |
| 353 | mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, |
| 354 | A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK); |
| 355 | |
| 356 | /* clear DSM by default */ |
| 357 | val = mmio_read_32(IMX_GPC_BASE + SLPCR); |
| 358 | val &= ~SLPCR_EN_DSM; |
| 359 | /* enable the fast wakeup wait/stop mode */ |
| 360 | val |= SLPCR_A53_FASTWUP_WAIT_MODE; |
| 361 | val |= SLPCR_A53_FASTWUP_STOP_MODE; |
| 362 | /* clear the RBC */ |
| 363 | val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT); |
| 364 | /* set the STBY_COUNT to 0x5, (128 * 30)us */ |
| 365 | val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT); |
| 366 | val |= (0x5 << SLPCR_STBY_COUNT_SHFT); |
| 367 | mmio_write_32(IMX_GPC_BASE + SLPCR, val); |
| 368 | |
| 369 | /* |
| 370 | * USB PHY power up needs to make sure RESET bit in SRC is clear, |
| 371 | * otherwise, the PU power up bit in GPC will NOT self-cleared. |
| 372 | * only need to do it once. |
| 373 | */ |
| 374 | mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); |
| 375 | mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); |
| 376 | |
| 377 | /* enable all the power domain by default */ |
| 378 | for (i = 0; i < 101; i++) { |
| 379 | mmio_write_32(IMX_CCM_BASE + CCGR(i), 0x3); |
| 380 | } |
| 381 | |
| 382 | for (i = 0; i < 20; i++) { |
| 383 | imx_gpc_pm_domain_enable(i, true); |
| 384 | } |
| 385 | } |