| Mario Bălănică | c883ce0 | 2023-12-02 03:08:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2024, Mario Bălănică <mariobalanica02@gmail.com> |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef RPI_HW_H |
| 9 | #define RPI_HW_H |
| 10 | |
| 11 | #include <lib/utils_def.h> |
| 12 | |
| 13 | /* |
| 14 | * Peripherals |
| 15 | */ |
| 16 | |
| 17 | #define RPI_IO_BASE ULL(0x1000000000) |
| 18 | #define RPI_IO_SIZE ULL(0x1000000000) |
| 19 | |
| 20 | /* |
| 21 | * ARM <-> VideoCore mailboxes |
| 22 | */ |
| 23 | #define RPI3_MBOX_BASE (RPI_IO_BASE + ULL(0x7c013880)) |
| 24 | |
| 25 | /* |
| 26 | * Power management, reset controller, watchdog. |
| 27 | */ |
| 28 | #define RPI3_PM_BASE (RPI_IO_BASE + ULL(0x7d200000)) |
| 29 | |
| 30 | /* |
| 31 | * Hardware random number generator. |
| 32 | */ |
| 33 | #define RPI3_RNG_BASE (RPI_IO_BASE + ULL(0x7d208000)) |
| 34 | |
| 35 | /* |
| 36 | * PL011 system serial port |
| 37 | */ |
| 38 | #define RPI4_PL011_UART_BASE (RPI_IO_BASE + ULL(0x7d001000)) |
| 39 | #define RPI4_PL011_UART_CLOCK ULL(44000000) |
| 40 | |
| 41 | /* |
| 42 | * GIC interrupt controller |
| 43 | */ |
| 44 | #define RPI_HAVE_GIC |
| 45 | #define RPI4_GIC_GICD_BASE (RPI_IO_BASE + ULL(0x7fff9000)) |
| 46 | #define RPI4_GIC_GICC_BASE (RPI_IO_BASE + ULL(0x7fffa000)) |
| 47 | |
| 48 | #define RPI4_LOCAL_CONTROL_BASE_ADDRESS (RPI_IO_BASE + ULL(0x7c280000)) |
| 49 | #define RPI4_LOCAL_CONTROL_PRESCALER (RPI_IO_BASE + ULL(0x7c280008)) |
| 50 | |
| Mario Bălănică | da8a390 | 2024-03-06 06:10:52 +0200 | [diff] [blame] | 51 | /* |
| 52 | * PCI Express |
| 53 | */ |
| 54 | #define RPI_PCIE_RC_BASES RPI_IO_BASE + ULL(0x00100000), \ |
| 55 | RPI_IO_BASE + ULL(0x00110000), \ |
| 56 | RPI_IO_BASE + ULL(0x00120000) |
| 57 | |
| Mario Bălănică | c883ce0 | 2023-12-02 03:08:02 +0200 | [diff] [blame] | 58 | #endif /* RPI_HW_H */ |