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git01.mediatek.com / filogic / atf / 2bdcb1548f889394279dec8c3f8b5707cadb68a3 / . / plat / intel / soc / n5x / platform.mk
blob: 4770f8d3e87724ac178b614c66c6a5deb45de730 [file] [log] [blame]
Sieu Mun Tang8881ad02022-03-07 12:04:59 +0800[diff] [blame]1#
Sieu Mun Tangd52f2482024-10-24 22:16:50 +0800[diff] [blame]2# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3# Copyright (c) 2024, Altera Corporation. All rights reserved.
Sieu Mun Tang8881ad02022-03-07 12:04:59 +0800[diff] [blame]4#
5# SPDX-License-Identifier: BSD-3-Clause
6#
7
8PLAT_INCLUDES := \
9 -Iplat/intel/soc/n5x/include/ \
10 -Iplat/intel/soc/common/drivers/ \
11 -Iplat/intel/soc/common/include/
12
13# Include GICv2 driver files
14include drivers/arm/gic/v2/gicv2.mk
15DM_GICv2_SOURCES := \
16 ${GICV2_SOURCES} \
17 plat/common/plat_gicv2.c
18
19
20PLAT_BL_COMMON_SOURCES := \
21 ${DM_GICv2_SOURCES} \
22 drivers/delay_timer/delay_timer.c \
23 drivers/delay_timer/generic_delay_timer.c \
24 drivers/ti/uart/aarch64/16550_console.S \
25 lib/xlat_tables/aarch64/xlat_tables.c \
26 lib/xlat_tables/xlat_tables_common.c \
27 plat/intel/soc/common/aarch64/platform_common.c \
28 plat/intel/soc/common/aarch64/plat_helpers.S \
Boon Khai Ng1e5550b2021-05-21 22:56:37 +0800[diff] [blame]29 plat/intel/soc/common/socfpga_delay_timer.c \
30 plat/intel/soc/common/drivers/ccu/ncore_ccu.c
Sieu Mun Tang8881ad02022-03-07 12:04:59 +0800[diff] [blame]31
32BL2_SOURCES +=
33
34BL31_SOURCES += \
35 drivers/arm/cci/cci.c \
36 lib/cpus/aarch64/aem_generic.S \
37 lib/cpus/aarch64/cortex_a53.S \
38 plat/common/plat_psci_common.c \
39 plat/intel/soc/n5x/bl31_plat_setup.c \
Sieu Mun Tangf48707a2022-06-23 18:05:02 +0800[diff] [blame]40 plat/intel/soc/n5x/soc/n5x_clock_manager.c \
Sieu Mun Tang8881ad02022-03-07 12:04:59 +0800[diff] [blame]41 plat/intel/soc/common/socfpga_psci.c \
42 plat/intel/soc/common/socfpga_sip_svc.c \
Sieu Mun Tang044ed482022-05-11 10:45:19 +0800[diff] [blame]43 plat/intel/soc/common/socfpga_sip_svc_v2.c \
Sieu Mun Tang8881ad02022-03-07 12:04:59 +0800[diff] [blame]44 plat/intel/soc/common/socfpga_topology.c \
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800[diff] [blame]45 plat/intel/soc/common/sip/socfpga_sip_ecc.c \
Sieu Mun Tang8881ad02022-03-07 12:04:59 +0800[diff] [blame]46 plat/intel/soc/common/sip/socfpga_sip_fcs.c \
47 plat/intel/soc/common/soc/socfpga_mailbox.c \
48 plat/intel/soc/common/soc/socfpga_reset_manager.c
49
Sieu Mun Tangd52f2482024-10-24 22:16:50 +0800[diff] [blame]50# Don't have the Linux kernel as a BL33 image by default
51ARM_LINUX_KERNEL_AS_BL33 := 0
52$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
53$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
Jit Loon Limc5a3e3a2023-10-16 00:19:34 +0800[diff] [blame]54$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
55
Sieu Mun Tangd52f2482024-10-24 22:16:50 +0800[diff] [blame]56# Configs for Boot Source
57SOCFPGA_BOOT_SOURCE_SDMMC ?= 0
58SOCFPGA_BOOT_SOURCE_QSPI ?= 0
59SOCFPGA_BOOT_SOURCE_NAND ?= 0
60
61$(eval $(call assert_booleans,\
62 $(sort \
63 SOCFPGA_BOOT_SOURCE_SDMMC \
64 SOCFPGA_BOOT_SOURCE_QSPI \
65 SOCFPGA_BOOT_SOURCE_NAND \
66)))
67$(eval $(call add_defines,\
68 $(sort \
69 SOCFPGA_BOOT_SOURCE_SDMMC \
70 SOCFPGA_BOOT_SOURCE_QSPI \
71 SOCFPGA_BOOT_SOURCE_NAND \
72)))
73
Sieu Mun Tang8881ad02022-03-07 12:04:59 +0800[diff] [blame]74PROGRAMMABLE_RESET_ADDRESS := 0
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600[diff] [blame]75RESET_TO_BL2 := 1
Sieu Mun Tang8881ad02022-03-07 12:04:59 +0800[diff] [blame]76BL2_INV_DCACHE := 0
Sieu Mun Tang8881ad02022-03-07 12:04:59 +0800[diff] [blame]77USE_COHERENT_MEM := 1