| Govindraj Raja | e48c36a | 2024-06-04 11:05:26 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #if __aarch64__ |
| 8 | |
| 9 | #include <aem_generic.h> |
| 10 | #include <arch_helpers.h> |
| 11 | #include <cortex_a35.h> |
| 12 | #include <cortex_a53.h> |
| 13 | #include <cortex_a57.h> |
| 14 | #include <cortex_a72.h> |
| 15 | #include <cortex_a73.h> |
| 16 | #include <cortex_a78_ae.h> |
| 17 | #include <drivers/arm/fvp/fvp_cpu_pwr.h> |
| 18 | #include <lib/utils_def.h> |
| 19 | #include <neoverse_e1.h> |
| 20 | |
| 21 | bool check_cpupwrctrl_el1_is_available(void) |
| 22 | { |
| 23 | /* Poupulate list of CPU midr that doesn't support CPUPWRCTL_EL1 */ |
| 24 | const unsigned int midr_no_cpupwrctl[] = { |
| 25 | BASE_AEM_MIDR, |
| 26 | CORTEX_A35_MIDR, |
| 27 | CORTEX_A53_MIDR, |
| 28 | CORTEX_A57_MIDR, |
| 29 | CORTEX_A72_MIDR, |
| 30 | CORTEX_A73_MIDR, |
| 31 | CORTEX_A78_AE_MIDR, |
| 32 | NEOVERSE_E1_MIDR |
| 33 | }; |
| 34 | unsigned int midr = (unsigned int)read_midr(); |
| 35 | |
| 36 | for (unsigned int i = 0U; i < ARRAY_SIZE(midr_no_cpupwrctl); i++) { |
| 37 | if (midr_no_cpupwrctl[i] == midr) { |
| 38 | return false; |
| 39 | } |
| 40 | } |
| 41 | |
| 42 | return true; |
| 43 | } |
| 44 | |
| 45 | #endif /* __arch64__ */ |