Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 1 | /* |
Vignesh Radhakrishnan | 3ad7983 | 2017-12-11 13:17:58 -0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef T194_NVG_H |
| 8 | #define T194_NVG_H |
| 9 | |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 12 | /** |
| 13 | * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). |
| 14 | * Official documentation for this interface is included as part |
| 15 | * of the T194 TRM. |
| 16 | */ |
| 17 | |
| 18 | /** |
| 19 | * Current version - Major version increments may break backwards |
| 20 | * compatiblity and binary compatibility. Minor version increments |
| 21 | * occur when there is only new functionality. |
| 22 | */ |
| 23 | enum { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 24 | TEGRA_NVG_VERSION_MAJOR = U(6), |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 25 | TEGRA_NVG_VERSION_MINOR = U(7) |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 26 | }; |
| 27 | |
| 28 | typedef enum { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 29 | TEGRA_NVG_CHANNEL_VERSION = U(0), |
| 30 | TEGRA_NVG_CHANNEL_POWER_PERF = U(1), |
| 31 | TEGRA_NVG_CHANNEL_POWER_MODES = U(2), |
| 32 | TEGRA_NVG_CHANNEL_WAKE_TIME = U(3), |
| 33 | TEGRA_NVG_CHANNEL_CSTATE_INFO = U(4), |
| 34 | TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = U(5), |
| 35 | TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = U(6), |
| 36 | TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = U(8), |
| 37 | TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = U(10), |
| 38 | TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = U(11), |
| 39 | TEGRA_NVG_CHANNEL_NUM_CORES = U(20), |
| 40 | TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID = U(21), |
| 41 | TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING = U(22), |
| 42 | TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR = U(23), |
| 43 | TEGRA_NVG_CHANNEL_SHUTDOWN = U(42), |
| 44 | TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = U(43), |
| 45 | TEGRA_NVG_CHANNEL_ONLINE_CORE = U(44), |
| 46 | TEGRA_NVG_CHANNEL_CC3_CTRL = U(45), |
| 47 | TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = U(49), |
| 48 | TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = U(50), |
| 49 | TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = U(53), |
| 50 | TEGRA_NVG_CHANNEL_SECURITY_CONFIG = U(54), |
| 51 | TEGRA_NVG_CHANNEL_DEBUG_CONFIG = U(55), |
| 52 | TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = U(56), |
| 53 | TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = U(57), |
| 54 | TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = U(58), |
| 55 | TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = U(59), |
| 56 | TEGRA_NVG_CHANNEL_DDA_MCF_ISO = U(60), |
| 57 | TEGRA_NVG_CHANNEL_DDA_MCF_SISO = U(61), |
| 58 | TEGRA_NVG_CHANNEL_DDA_MCF_NISO = U(62), |
| 59 | TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = U(63), |
| 60 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = U(64), |
| 61 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = U(65), |
| 62 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = U(66), |
| 63 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = U(67), |
| 64 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = U(68), |
| 65 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = U(69), |
| 66 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = U(70), |
| 67 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = U(71), |
| 68 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = U(72), |
| 69 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = U(73), |
| 70 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = U(74), |
| 71 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = U(75), |
| 72 | TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = U(76), |
| 73 | TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = U(77), |
| 74 | TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = U(78), |
| 75 | TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = U(79), |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 76 | TEGRA_NVG_CHANNEL_RT_SAFE_MASK = U(80), |
| 77 | TEGRA_NVG_CHANNEL_RT_WINDOW_US = U(81), |
| 78 | TEGRA_NVG_CHANNEL_RT_FWD_PROGRESS_US = U(82), |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 79 | |
| 80 | TEGRA_NVG_CHANNEL_LAST_INDEX |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 81 | } tegra_nvg_channel_id_t; |
| 82 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 83 | typedef enum { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 84 | NVG_STAT_QUERY_SC7_ENTRIES = U(1), |
| 85 | NVG_STAT_QUERY_CC6_ENTRIES = U(6), |
| 86 | NVG_STAT_QUERY_CG7_ENTRIES = U(7), |
| 87 | NVG_STAT_QUERY_C6_ENTRIES = U(10), |
| 88 | NVG_STAT_QUERY_C7_ENTRIES = U(14), |
| 89 | NVG_STAT_QUERY_SC7_RESIDENCY_SUM = U(32), |
| 90 | NVG_STAT_QUERY_CC6_RESIDENCY_SUM = U(41), |
| 91 | NVG_STAT_QUERY_CG7_RESIDENCY_SUM = U(46), |
| 92 | NVG_STAT_QUERY_C6_RESIDENCY_SUM = U(51), |
| 93 | NVG_STAT_QUERY_C7_RESIDENCY_SUM = U(56), |
| 94 | NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = U(60), |
| 95 | NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = U(61), |
| 96 | NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = U(62), |
| 97 | NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = U(63), |
| 98 | NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = U(64), |
| 99 | NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = U(70), |
| 100 | NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = U(71), |
| 101 | NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = U(72), |
| 102 | NVG_STAT_QUERY_C6_EXIT_TIME_SUM = U(73), |
| 103 | NVG_STAT_QUERY_C7_EXIT_TIME_SUM = U(74), |
| 104 | NVG_STAT_QUERY_SC7_ENTRY_LAST = U(80), |
| 105 | NVG_STAT_QUERY_CC6_ENTRY_LAST = U(81), |
| 106 | NVG_STAT_QUERY_CG7_ENTRY_LAST = U(82), |
| 107 | NVG_STAT_QUERY_C6_ENTRY_LAST = U(83), |
| 108 | NVG_STAT_QUERY_C7_ENTRY_LAST = U(84), |
| 109 | NVG_STAT_QUERY_SC7_EXIT_LAST = U(90), |
| 110 | NVG_STAT_QUERY_CC6_EXIT_LAST = U(91), |
| 111 | NVG_STAT_QUERY_CG7_EXIT_LAST = U(92), |
| 112 | NVG_STAT_QUERY_C6_EXIT_LAST = U(93), |
| 113 | NVG_STAT_QUERY_C7_EXIT_LAST = U(94) |
| 114 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 115 | } tegra_nvg_stat_query_t; |
| 116 | |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 117 | typedef enum { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 118 | TEGRA_NVG_CORE_C0 = U(0), |
| 119 | TEGRA_NVG_CORE_C1 = U(1), |
| 120 | TEGRA_NVG_CORE_C6 = U(6), |
| 121 | TEGRA_NVG_CORE_C7 = U(7), |
| 122 | TEGRA_NVG_CORE_WARMRSTREQ = U(8) |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 123 | } tegra_nvg_core_sleep_state_t; |
| 124 | |
| 125 | typedef enum { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 126 | TEGRA_NVG_SHUTDOWN = U(0), |
| 127 | TEGRA_NVG_REBOOT = U(1) |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 128 | } tegra_nvg_shutdown_reboot_state_t; |
| 129 | |
| 130 | typedef enum { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 131 | TEGRA_NVG_CLUSTER_CC0 = U(0), |
| 132 | TEGRA_NVG_CLUSTER_AUTO_CC1 = U(1), |
| 133 | TEGRA_NVG_CLUSTER_CC6 = U(6) |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 134 | } tegra_nvg_cluster_sleep_state_t; |
| 135 | |
| 136 | typedef enum { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 137 | TEGRA_NVG_CG_CG0 = U(0), |
| 138 | TEGRA_NVG_CG_CG7 = U(7) |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 139 | } tegra_nvg_cluster_group_sleep_state_t; |
| 140 | |
| 141 | typedef enum { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 142 | TEGRA_NVG_SYSTEM_SC0 = U(0), |
| 143 | TEGRA_NVG_SYSTEM_SC7 = U(7), |
| 144 | TEGRA_NVG_SYSTEM_SC8 = U(8) |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 145 | } tegra_nvg_system_sleep_state_t; |
| 146 | |
| 147 | // --------------------------------------------------------------------------- |
| 148 | // NVG Data subformats |
| 149 | // --------------------------------------------------------------------------- |
| 150 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 151 | typedef union { |
| 152 | uint64_t flat; |
| 153 | struct nvg_version_channel_t { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 154 | uint32_t minor_version : U(32); |
| 155 | uint32_t major_version : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 156 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 157 | } nvg_version_data_t; |
| 158 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 159 | typedef union { |
| 160 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 161 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 162 | uint32_t perf_per_watt : U(1); |
| 163 | uint32_t reserved_31_1 : U(31); |
| 164 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 165 | } bits; |
| 166 | } nvg_power_perf_channel_t; |
| 167 | |
| 168 | typedef union { |
| 169 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 170 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 171 | uint32_t low_battery : U(1); |
| 172 | uint32_t reserved_1_1 : U(1); |
| 173 | uint32_t battery_save : U(1); |
| 174 | uint32_t reserved_31_3 : U(29); |
| 175 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 176 | } bits; |
| 177 | } nvg_power_modes_channel_t; |
| 178 | |
| 179 | typedef union nvg_channel_1_data_u { |
| 180 | uint64_t flat; |
| 181 | struct nvg_channel_1_data_s { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 182 | uint32_t perf_per_watt_mode : U(1); |
| 183 | uint32_t reserved_31_1 : U(31); |
| 184 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 185 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 186 | } nvg_channel_1_data_t; |
| 187 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 188 | typedef union { |
| 189 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 190 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 191 | uint32_t gpu_ways : U(5); |
| 192 | uint32_t reserved_7_5 : U(3); |
| 193 | uint32_t gpu_only_ways : U(5); |
| 194 | uint32_t reserved_31_13 : U(19); |
| 195 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 196 | } bits; |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 197 | } nvg_ccplex_cache_control_channel_t; |
| 198 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 199 | typedef union nvg_channel_2_data_u { |
| 200 | uint64_t flat; |
| 201 | struct nvg_channel_2_data_s { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 202 | uint32_t reserved_1_0 : U(2); |
| 203 | uint32_t battery_saver_mode : U(1); |
| 204 | uint32_t reserved_31_3 : U(29); |
| 205 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 206 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 207 | } nvg_channel_2_data_t; |
| 208 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 209 | typedef union { |
| 210 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 211 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 212 | uint32_t wake_time : U(32); |
| 213 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 214 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 215 | } nvg_wake_time_channel_t; |
| 216 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 217 | typedef union { |
| 218 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 219 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 220 | uint32_t cluster_state : U(3); |
| 221 | uint32_t reserved_6_3 : U(4); |
| 222 | uint32_t update_cluster : U(1); |
| 223 | uint32_t cg_cstate : U(3); |
| 224 | uint32_t reserved_14_11 : U(4); |
| 225 | uint32_t update_cg : U(1); |
| 226 | uint32_t system_cstate : U(4); |
| 227 | uint32_t reserved_22_20 : U(3); |
| 228 | uint32_t update_system : U(1); |
| 229 | uint32_t reserved_30_24 : U(7); |
| 230 | uint32_t update_wake_mask : U(1); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 231 | union { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 232 | uint32_t flat : U(32); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 233 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 234 | uint32_t vfiq : U(1); |
| 235 | uint32_t virq : U(1); |
| 236 | uint32_t fiq : U(1); |
| 237 | uint32_t irq : U(1); |
| 238 | uint32_t serror : U(1); |
| 239 | uint32_t reserved_10_5 : U(6); |
| 240 | uint32_t fiqout : U(1); |
| 241 | uint32_t irqout : U(1); |
| 242 | uint32_t reserved_31_13 : U(19); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 243 | } carmel; |
| 244 | } wake_mask; |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 245 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 246 | } nvg_cstate_info_channel_t; |
| 247 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 248 | typedef union { |
| 249 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 250 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 251 | uint32_t crossover_value : U(32); |
| 252 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 253 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 254 | } nvg_lower_bound_channel_t; |
| 255 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 256 | typedef union { |
| 257 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 258 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 259 | uint32_t unit_id : U(4); |
| 260 | uint32_t reserved_15_4 : U(12); |
| 261 | uint32_t stat_id : U(16); |
| 262 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 263 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 264 | } nvg_cstate_stat_query_channel_t; |
| 265 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 266 | typedef union { |
| 267 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 268 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 269 | uint32_t num_cores : U(4); |
| 270 | uint32_t reserved_31_4 : U(28); |
| 271 | uint32_t reserved_63_32 : U(32); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 272 | } bits; |
| 273 | } nvg_num_cores_channel_t; |
| 274 | |
| 275 | typedef union { |
| 276 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 277 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 278 | uint32_t unique_core_id : U(3); |
| 279 | uint32_t reserved_31_3 : U(29); |
| 280 | uint32_t reserved_63_32 : U(32); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 281 | } bits; |
| 282 | } nvg_unique_logical_id_channel_t; |
| 283 | |
| 284 | typedef union { |
| 285 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 286 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 287 | uint32_t lcore0_pcore_id : U(4); |
| 288 | uint32_t lcore1_pcore_id : U(4); |
| 289 | uint32_t lcore2_pcore_id : U(4); |
| 290 | uint32_t lcore3_pcore_id : U(4); |
| 291 | uint32_t lcore4_pcore_id : U(4); |
| 292 | uint32_t lcore5_pcore_id : U(4); |
| 293 | uint32_t lcore6_pcore_id : U(4); |
| 294 | uint32_t lcore7_pcore_id : U(4); |
| 295 | uint32_t reserved_63_32 : U(32); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 296 | } bits; |
| 297 | } nvg_logical_to_physical_mappings_channel_t; |
| 298 | |
| 299 | typedef union { |
| 300 | uint64_t flat; |
| 301 | struct nvg_logical_to_mpidr_channel_write_t { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 302 | uint32_t lcore_id : U(3); |
| 303 | uint32_t reserved_31_3 : U(29); |
| 304 | uint32_t reserved_63_32 : U(32); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 305 | } write; |
| 306 | struct nvg_logical_to_mpidr_channel_read_t { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 307 | uint32_t mpidr : U(32); |
| 308 | uint32_t reserved_63_32 : U(32); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 309 | } read; |
| 310 | } nvg_logical_to_mpidr_channel_t; |
| 311 | |
| 312 | typedef union { |
| 313 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 314 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 315 | uint32_t is_sc7_allowed : U(1); |
| 316 | uint32_t reserved_31_1 : U(31); |
| 317 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 318 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 319 | } nvg_is_sc7_allowed_channel_t; |
| 320 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 321 | typedef union { |
| 322 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 323 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 324 | uint32_t core_id : U(4); |
| 325 | uint32_t reserved_31_4 : U(28); |
| 326 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 327 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 328 | } nvg_core_online_channel_t; |
| 329 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 330 | typedef union { |
| 331 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 332 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 333 | uint32_t freq_req : U(9); |
| 334 | uint32_t reserved_30_9 : U(22); |
| 335 | uint32_t enable : U(1); |
| 336 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 337 | } bits; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 338 | } nvg_cc3_control_channel_t; |
| 339 | |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 340 | typedef enum { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 341 | TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = U(0), |
| 342 | TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = U(1), |
| 343 | TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = U(2), |
| 344 | TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = U(3), |
| 345 | TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = U(4), |
| 346 | TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = U(5), |
| 347 | TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = U(6), |
| 348 | TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = U(7), |
| 349 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = U(8), |
| 350 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = U(9), |
| 351 | TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = U(10), |
| 352 | TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = U(11), |
| 353 | TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = U(12), |
| 354 | TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = U(13), |
| 355 | TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = U(14), |
| 356 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = U(15), |
| 357 | TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = U(16), |
| 358 | TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = U(17), |
| 359 | TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = U(18), |
| 360 | TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = U(19), |
| 361 | TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = U(20), |
| 362 | TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = U(21), |
| 363 | TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = U(22), |
| 364 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = U(23), |
| 365 | TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = U(24), |
| 366 | TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = U(25), |
| 367 | TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = U(26), |
| 368 | TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = U(27), |
| 369 | TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = U(28), |
| 370 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = U(29), |
| 371 | TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = U(30), |
| 372 | TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = U(31), |
| 373 | TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = U(32), |
| 374 | TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = U(33), |
| 375 | TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = U(34), |
| 376 | TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = U(35), |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 377 | TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 378 | } tegra_nvg_channel_update_gsc_gsc_enum_t; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 379 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 380 | typedef union { |
| 381 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 382 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 383 | uint32_t gsc_enum : U(16); |
| 384 | uint32_t reserved_31_16 : U(16); |
| 385 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 386 | } bits; |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 387 | } nvg_update_ccplex_gsc_channel_t; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 388 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 389 | typedef union { |
| 390 | uint64_t flat; |
| 391 | struct nvg_security_config_channel_t { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 392 | uint32_t strict_checking_enabled : U(1); |
| 393 | uint32_t strict_checking_locked : U(1); |
| 394 | uint32_t reserved_31_2 : U(30); |
| 395 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 396 | } bits; |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 397 | } nvg_security_config_t; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 398 | |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 399 | typedef union { |
| 400 | uint64_t flat; |
| 401 | struct nvg_shutdown_channel_t { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 402 | uint32_t reboot : U(1); |
| 403 | uint32_t reserved_31_1 : U(31); |
| 404 | uint32_t reserved_63_32 : U(32); |
Steven Kao | 2a6559a | 2017-11-08 11:33:56 +0800 | [diff] [blame] | 405 | } bits; |
Steven Kao | 6f373a2 | 2017-09-29 18:09:17 +0800 | [diff] [blame] | 406 | } nvg_shutdown_t; |
Steven Kao | 2cdb678 | 2017-01-05 17:04:40 +0800 | [diff] [blame] | 407 | |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 408 | typedef union { |
| 409 | uint64_t flat; |
| 410 | struct nvg_debug_config_channel_t { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 411 | uint32_t enter_debug_state_on_mca : U(1); |
| 412 | uint32_t reserved_31_1 : U(31); |
| 413 | uint32_t reserved_63_32 : U(32); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 414 | } bits; |
| 415 | } nvg_debug_config_t; |
| 416 | |
| 417 | typedef union { |
| 418 | uint64_t flat; |
Kalyani Chidambaram | 35319c2 | 2018-09-19 15:51:46 -0700 | [diff] [blame] | 419 | struct { |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 420 | uint32_t uncorr : U(1); |
| 421 | uint32_t corr : U(1); |
| 422 | uint32_t reserved_31_2 : U(30); |
| 423 | uint32_t reserved_63_32 : U(32); |
Varun Wadekar | 29e5a11 | 2018-04-10 15:49:57 -0700 | [diff] [blame] | 424 | } bits; |
| 425 | } nvg_hsm_error_ctrl_channel_t; |
| 426 | |
| 427 | extern nvg_debug_config_t nvg_debug_config; |
| 428 | |
Varun Wadekar | fc463c5 | 2018-05-25 16:17:53 -0700 | [diff] [blame] | 429 | #endif /* T194_NVG_H */ |