| Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __PLAT_DEF_H__ |
| 32 | #define __PLAT_DEF_H__ |
| 33 | |
| 34 | /* Special value used to verify platform parameters from BL2 to BL3-1 */ |
| 35 | #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL |
| 36 | |
| 37 | #define CCI400_BASE 0xffb90000 |
| 38 | #define CCI400_SIZE 0x10000 |
| 39 | |
| 40 | #define GIC400_BASE 0xffb70000 |
| 41 | #define GIC400_SIZE 0x10000 |
| 42 | |
| 43 | #define STIME_BASE 0xff830000 |
| 44 | #define STIME_SIZE 0x10000 |
| 45 | |
| 46 | #define CRU_BASE 0xff760000 |
| 47 | #define CRU_SIZE 0x10000 |
| 48 | |
| 49 | #define GRF_BASE 0xff770000 |
| 50 | #define GRF_SIZE 0x10000 |
| 51 | |
| 52 | #define SGRF_BASE 0xff740000 |
| 53 | #define SGRF_SIZE 0x10000 |
| 54 | |
| 55 | #define PMU_BASE 0xff730000 |
| 56 | #define PMU_GRF_BASE 0xff738000 |
| 57 | #define PMU_SIZE 0x10000 |
| 58 | |
| 59 | #define RK_INTMEM_BASE 0xff8c0000 |
| 60 | #define RK_INTMEM_SIZE 0x10000 |
| 61 | |
| 62 | #define UART_DBG_BASE 0xff690000 |
| 63 | #define UART_DBG_SIZE 0x10000 |
| 64 | |
| 65 | #define CRU_BASE 0xff760000 |
| 66 | |
| 67 | #define PMUSRAM_BASE 0xff720000 |
| 68 | #define PMUSRAM_SIZE 0x10000 |
| 69 | #define PMUSRAM_RSIZE 0x1000 |
| 70 | |
| 71 | #define DDR_PCTL_BASE 0xff610000 |
| 72 | #define DDR_PCTL_SIZE 0x10000 |
| 73 | |
| 74 | #define DDR_PHY_BASE 0xff620000 |
| 75 | #define DDR_PHY_SIZE 0x10000 |
| 76 | |
| 77 | #define SERVICE_BUS_BASE 0xffac0000 |
| 78 | #define SERVICE_BUS_SISE 0x50000 |
| 79 | |
| 80 | #define COLD_BOOT_BASE 0xffff0000 |
| 81 | /************************************************************************** |
| 82 | * UART related constants |
| 83 | **************************************************************************/ |
| 84 | #define RK3368_UART2_BASE UART_DBG_BASE |
| 85 | #define RK3368_BAUDRATE 115200 |
| 86 | #define RK3368_UART_CLOCK 24000000 |
| 87 | |
| 88 | /****************************************************************************** |
| 89 | * System counter frequency related constants |
| 90 | ******************************************************************************/ |
| 91 | #define SYS_COUNTER_FREQ_IN_TICKS 24000000 |
| 92 | #define SYS_COUNTER_FREQ_IN_MHZ 24 |
| 93 | |
| 94 | /****************************************************************************** |
| 95 | * GIC-400 & interrupt handling related constants |
| 96 | ******************************************************************************/ |
| 97 | |
| 98 | /* Base rk_platform compatible GIC memory map */ |
| 99 | #define RK3368_GICD_BASE (GIC400_BASE + 0x1000) |
| 100 | #define RK3368_GICC_BASE (GIC400_BASE + 0x2000) |
| 101 | #define RK3368_GICR_BASE 0 /* no GICR in GIC-400 */ |
| 102 | |
| 103 | /***************************************************************************** |
| 104 | * CCI-400 related constants |
| 105 | ******************************************************************************/ |
| 106 | #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 3 |
| 107 | #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 4 |
| 108 | |
| 109 | /****************************************************************************** |
| 110 | * cpu up status |
| 111 | ******************************************************************************/ |
| 112 | #define PMU_CPU_HOTPLUG 0xdeadbeaf |
| 113 | #define PMU_CPU_AUTO_PWRDN 0xabcdef12 |
| 114 | |
| 115 | /****************************************************************************** |
| 116 | * sgi, ppi |
| 117 | ******************************************************************************/ |
| 118 | #define RK_IRQ_SEC_PHY_TIMER 29 |
| 119 | |
| 120 | #define RK_IRQ_SEC_SGI_0 8 |
| 121 | #define RK_IRQ_SEC_SGI_1 9 |
| 122 | #define RK_IRQ_SEC_SGI_2 10 |
| 123 | #define RK_IRQ_SEC_SGI_3 11 |
| 124 | #define RK_IRQ_SEC_SGI_4 12 |
| 125 | #define RK_IRQ_SEC_SGI_5 13 |
| 126 | #define RK_IRQ_SEC_SGI_6 14 |
| 127 | #define RK_IRQ_SEC_SGI_7 15 |
| 128 | |
| 129 | /* |
| 130 | * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 |
| 131 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 132 | * as Group 0 interrupts. |
| 133 | */ |
| 134 | #define RK_G1S_IRQS (RK_IRQ_SEC_PHY_TIMER) |
| 135 | |
| 136 | #endif /* __PLAT_DEF_H__ */ |