blob: d411ad021219dfba6566abedfc2cc2874b38c928 [file] [log] [blame]
Achin Gupta7c88f3f2014-02-18 18:09:12 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handleyed6ff952014-05-14 17:44:19 +010031#include <platform_def.h>
Achin Gupta7c88f3f2014-02-18 18:09:12 +000032
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000035ENTRY(tsp_entrypoint)
36
Achin Gupta7c88f3f2014-02-18 18:09:12 +000037
38MEMORY {
Sandrine Bailleux5ac3cc92014-05-20 17:22:24 +010039 RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
Achin Gupta7c88f3f2014-02-18 18:09:12 +000040}
41
42
43SECTIONS
44{
45 . = BL32_BASE;
46 ASSERT(. == ALIGN(4096),
47 "BL32_BASE address is not aligned on a page boundary.")
48
49 ro . : {
50 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000051 *tsp_entrypoint.o(.text*)
52 *(.text*)
Achin Gupta7c88f3f2014-02-18 18:09:12 +000053 *(.rodata*)
54 *(.vectors)
55 __RO_END_UNALIGNED__ = .;
56 /*
57 * Memory page(s) mapped to this section will be marked as
58 * read-only, executable. No RW data from the next section must
59 * creep in. Ensure the rest of the current memory page is unused.
60 */
61 . = NEXT(4096);
62 __RO_END__ = .;
63 } >RAM
64
65 .data . : {
66 __DATA_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000067 *(.data*)
Achin Gupta7c88f3f2014-02-18 18:09:12 +000068 __DATA_END__ = .;
69 } >RAM
70
Dan Handley4fd2f5c2014-08-04 11:41:20 +010071#ifdef TSP_PROGBITS_LIMIT
72 ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +010073#endif
74
Achin Gupta7c88f3f2014-02-18 18:09:12 +000075 stacks (NOLOAD) : {
76 __STACKS_START__ = .;
77 *(tzfw_normal_stacks)
78 __STACKS_END__ = .;
79 } >RAM
80
81 /*
82 * The .bss section gets initialised to 0 at runtime.
83 * Its base address must be 16-byte aligned.
84 */
85 .bss : ALIGN(16) {
86 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000087 *(SORT_BY_ALIGNMENT(.bss*))
Achin Gupta7c88f3f2014-02-18 18:09:12 +000088 *(COMMON)
89 __BSS_END__ = .;
90 } >RAM
91
92 /*
93 * The xlat_table section is for full, aligned page tables (4K).
94 * Removing them from .bss avoids forcing 4K alignment on
95 * the .bss section and eliminates the unecessary zero init
96 */
97 xlat_table (NOLOAD) : {
98 *(xlat_table)
99 } >RAM
100
Soby Mathew2ae20432015-01-08 18:02:44 +0000101#if USE_COHERENT_MEM
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000102 /*
103 * The base address of the coherent memory section must be page-aligned (4K)
104 * to guarantee that the coherent data are stored on their own pages and
105 * are not mixed with normal data. This is required to set up the correct
106 * memory attributes for the coherent data page tables.
107 */
108 coherent_ram (NOLOAD) : ALIGN(4096) {
109 __COHERENT_RAM_START__ = .;
110 *(tzfw_coherent_mem)
111 __COHERENT_RAM_END_UNALIGNED__ = .;
112 /*
113 * Memory page(s) mapped to this section will be marked
114 * as device memory. No other unexpected data must creep in.
115 * Ensure the rest of the current memory page is unused.
116 */
117 . = NEXT(4096);
118 __COHERENT_RAM_END__ = .;
119 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000120#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000121
Sandrine Bailleuxe701e302014-05-20 17:28:25 +0100122 __BL32_END__ = .;
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000123
124 __BSS_SIZE__ = SIZEOF(.bss);
Soby Mathew2ae20432015-01-08 18:02:44 +0000125#if USE_COHERENT_MEM
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000126 __COHERENT_RAM_UNALIGNED_SIZE__ =
127 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000128#endif
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000129
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100130 ASSERT(. <= BL32_LIMIT, "BL3-2 image has exceeded its limit.")
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000131}