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Achin Guptaa4f50c22014-05-09 12:17:56 +01001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <bl_common.h>
32#include <arch.h>
33#include <tsp.h>
34#include <asm_macros.S>
35
36
37 /* ----------------------------------------------------
38 * The caller-saved registers x0-x18 and LR are saved
39 * here.
40 * ----------------------------------------------------
41 */
42
43#define SCRATCH_REG_SIZE #(20 * 8)
44
45 .macro save_caller_regs_and_lr
46 sub sp, sp, SCRATCH_REG_SIZE
47 stp x0, x1, [sp]
48 stp x2, x3, [sp, #0x10]
49 stp x4, x5, [sp, #0x20]
50 stp x6, x7, [sp, #0x30]
51 stp x8, x9, [sp, #0x40]
52 stp x10, x11, [sp, #0x50]
53 stp x12, x13, [sp, #0x60]
54 stp x14, x15, [sp, #0x70]
55 stp x16, x17, [sp, #0x80]
56 stp x18, x30, [sp, #0x90]
57 .endm
58
59 .macro restore_caller_regs_and_lr
60 ldp x0, x1, [sp]
61 ldp x2, x3, [sp, #0x10]
62 ldp x4, x5, [sp, #0x20]
63 ldp x6, x7, [sp, #0x30]
64 ldp x8, x9, [sp, #0x40]
65 ldp x10, x11, [sp, #0x50]
66 ldp x12, x13, [sp, #0x60]
67 ldp x14, x15, [sp, #0x70]
68 ldp x16, x17, [sp, #0x80]
69 ldp x18, x30, [sp, #0x90]
70 add sp, sp, SCRATCH_REG_SIZE
71 .endm
72
73 .globl tsp_exceptions
74
75 /* -----------------------------------------------------
76 * TSP exception handlers.
77 * -----------------------------------------------------
78 */
79 .section .vectors, "ax"; .align 11
80
81 .align 7
82tsp_exceptions:
83 /* -----------------------------------------------------
84 * Current EL with _sp_el0 : 0x0 - 0x180. No exceptions
85 * are expected and treated as irrecoverable errors.
86 * -----------------------------------------------------
87 */
88sync_exception_sp_el0:
89 wfi
90 b sync_exception_sp_el0
91 check_vector_size sync_exception_sp_el0
92
93 .align 7
94
95irq_sp_el0:
96 b irq_sp_el0
97 check_vector_size irq_sp_el0
98
99 .align 7
100fiq_sp_el0:
101 b fiq_sp_el0
102 check_vector_size fiq_sp_el0
103
104 .align 7
105serror_sp_el0:
106 b serror_sp_el0
107 check_vector_size serror_sp_el0
108
109
110 /* -----------------------------------------------------
111 * Current EL with SPx: 0x200 - 0x380. Only IRQs/FIQs
112 * are expected and handled
113 * -----------------------------------------------------
114 */
115 .align 7
116sync_exception_sp_elx:
117 wfi
118 b sync_exception_sp_elx
119 check_vector_size sync_exception_sp_elx
120
121 .align 7
122irq_sp_elx:
Achin Guptaed1744e2014-08-04 23:13:10 +0100123 /* Enable the SError interrupt */
124 msr daifclr, #DAIF_ABT_BIT
125
Soby Mathew9f71f702014-05-09 20:49:17 +0100126 save_caller_regs_and_lr
127 /* We just update some statistics in the handler */
128 bl tsp_irq_received
129 /* Hand over control to the normal world to handle the IRQ */
130 smc #0
131 /* The resume std smc starts from here */
132 restore_caller_regs_and_lr
133 eret
Achin Guptaa4f50c22014-05-09 12:17:56 +0100134 check_vector_size irq_sp_elx
135
136 .align 7
137fiq_sp_elx:
Achin Guptaed1744e2014-08-04 23:13:10 +0100138 /* Enable the SError interrupt */
139 msr daifclr, #DAIF_ABT_BIT
140
Achin Guptaa4f50c22014-05-09 12:17:56 +0100141 save_caller_regs_and_lr
142 bl tsp_fiq_handler
143 cbz x0, fiq_sp_elx_done
144
145 /*
146 * This FIQ was not targetted to S-EL1 so send it to
147 * the monitor and wait for execution to resume.
148 */
149 smc #0
150fiq_sp_elx_done:
151 restore_caller_regs_and_lr
152 eret
153 check_vector_size fiq_sp_elx
154
155 .align 7
156serror_sp_elx:
157 b serror_sp_elx
158 check_vector_size serror_sp_elx
159
160
161 /* -----------------------------------------------------
162 * Lower EL using AArch64 : 0x400 - 0x580. No exceptions
163 * are handled since TSP does not implement a lower EL
164 * -----------------------------------------------------
165 */
166 .align 7
167sync_exception_aarch64:
168 wfi
169 b sync_exception_aarch64
170 check_vector_size sync_exception_aarch64
171
172 .align 7
173irq_aarch64:
174 b irq_aarch64
175 check_vector_size irq_aarch64
176
177 .align 7
178fiq_aarch64:
179 b fiq_aarch64
180 check_vector_size fiq_aarch64
181
182 .align 7
183serror_aarch64:
184 b serror_aarch64
185 check_vector_size serror_aarch64
186
187
188 /* -----------------------------------------------------
189 * Lower EL using AArch32 : 0x600 - 0x780. No exceptions
190 * handled since the TSP does not implement a lower EL.
191 * -----------------------------------------------------
192 */
193 .align 7
194sync_exception_aarch32:
195 wfi
196 b sync_exception_aarch32
197 check_vector_size sync_exception_aarch32
198
199 .align 7
200irq_aarch32:
201 b irq_aarch32
202 check_vector_size irq_aarch32
203
204 .align 7
205fiq_aarch32:
206 b fiq_aarch32
207 check_vector_size fiq_aarch32
208
209 .align 7
210serror_aarch32:
211 b serror_aarch32
212 check_vector_size serror_aarch32
213 .align 7