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Achin Gupta76717892014-05-09 11:42:56 +01001/*
Dan Handleyeb839ce2015-03-23 18:13:33 +00002 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta76717892014-05-09 11:42:56 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta76717892014-05-09 11:42:56 +01005 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <debug.h>
Achin Gupta76717892014-05-09 11:42:56 +010010#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010011#include <platform_def.h>
Dan Handleye2c27f52014-08-01 17:58:27 +010012#include <tsp.h>
13#include "tsp_private.h"
Achin Gupta76717892014-05-09 11:42:56 +010014
15/*******************************************************************************
Soby Mathewbec98512015-09-03 18:29:38 +010016 * This function updates the TSP statistics for S-EL1 interrupts handled
17 * synchronously i.e the ones that have been handed over by the TSPD. It also
18 * keeps count of the number of times control was passed back to the TSPD
19 * after handling the interrupt. In the future it will be possible that the
20 * TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to
21 * return execution. This statistic will be useful to distinguish between these
22 * two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter
23 * contains the address of the instruction in normal world where this S-EL1
24 * interrupt was generated.
Achin Gupta76717892014-05-09 11:42:56 +010025 ******************************************************************************/
Soby Mathewbec98512015-09-03 18:29:38 +010026void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3)
Achin Gupta76717892014-05-09 11:42:56 +010027{
Soby Mathewda43b662015-07-08 21:45:46 +010028 uint32_t linear_id = plat_my_core_pos();
Achin Gupta76717892014-05-09 11:42:56 +010029
Soby Mathewbec98512015-09-03 18:29:38 +010030 tsp_stats[linear_id].sync_sel1_intr_count++;
31 if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN)
32 tsp_stats[linear_id].sync_sel1_intr_ret_count++;
Achin Gupta76717892014-05-09 11:42:56 +010033
Dan Handley91b624e2014-07-29 17:14:00 +010034#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
Achin Gupta76717892014-05-09 11:42:56 +010035 spin_lock(&console_lock);
Masahiro Yamadae93a0f42018-02-02 15:09:36 +090036 VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%llx\n",
Soby Mathewda43b662015-07-08 21:45:46 +010037 read_mpidr(), elr_el3);
Soby Mathewbec98512015-09-03 18:29:38 +010038 VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests,"
39 " %d sync s-el1 interrupt returns\n",
Soby Mathewda43b662015-07-08 21:45:46 +010040 read_mpidr(),
Soby Mathewbec98512015-09-03 18:29:38 +010041 tsp_stats[linear_id].sync_sel1_intr_count,
42 tsp_stats[linear_id].sync_sel1_intr_ret_count);
Achin Gupta76717892014-05-09 11:42:56 +010043 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +010044#endif
Achin Gupta76717892014-05-09 11:42:56 +010045}
46
Soby Mathewbc912822015-09-22 12:01:18 +010047/******************************************************************************
48 * This function is invoked when a non S-EL1 interrupt is received and causes
49 * the preemption of TSP. This function returns TSP_PREEMPTED and results
50 * in the control being handed over to EL3 for handling the interrupt.
51 *****************************************************************************/
52int32_t tsp_handle_preemption(void)
53{
54 uint32_t linear_id = plat_my_core_pos();
55
56 tsp_stats[linear_id].preempt_intr_count++;
57#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
58 spin_lock(&console_lock);
59 VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n",
60 read_mpidr(), tsp_stats[linear_id].preempt_intr_count);
61 spin_unlock(&console_lock);
62#endif
63 return TSP_PREEMPTED;
64}
65
Achin Gupta76717892014-05-09 11:42:56 +010066/*******************************************************************************
Soby Mathewbec98512015-09-03 18:29:38 +010067 * TSP interrupt handler is called as a part of both synchronous and
68 * asynchronous handling of TSP interrupts. Currently the physical timer
69 * interrupt is the only S-EL1 interrupt that this handler expects. It returns
70 * 0 upon successfully handling the expected interrupt and all other
71 * interrupts are treated as normal world or EL3 interrupts.
Achin Gupta76717892014-05-09 11:42:56 +010072 ******************************************************************************/
Soby Mathewbec98512015-09-03 18:29:38 +010073int32_t tsp_common_int_handler(void)
Achin Gupta76717892014-05-09 11:42:56 +010074{
Soby Mathewda43b662015-07-08 21:45:46 +010075 uint32_t linear_id = plat_my_core_pos(), id;
Achin Gupta76717892014-05-09 11:42:56 +010076
77 /*
78 * Get the highest priority pending interrupt id and see if it is the
79 * secure physical generic timer interrupt in which case, handle it.
80 * Otherwise throw this interrupt at the EL3 firmware.
Soby Mathewbc912822015-09-22 12:01:18 +010081 *
82 * There is a small time window between reading the highest priority
83 * pending interrupt and acknowledging it during which another
84 * interrupt of higher priority could become the highest pending
85 * interrupt. This is not expected to happen currently for TSP.
Achin Gupta76717892014-05-09 11:42:56 +010086 */
Dan Handley701fea72014-05-27 16:17:21 +010087 id = plat_ic_get_pending_interrupt_id();
Achin Gupta76717892014-05-09 11:42:56 +010088
89 /* TSP can only handle the secure physical timer interrupt */
Dan Handley4fd2f5c2014-08-04 11:41:20 +010090 if (id != TSP_IRQ_SEC_PHY_TIMER)
Soby Mathewbc912822015-09-22 12:01:18 +010091 return tsp_handle_preemption();
Achin Gupta76717892014-05-09 11:42:56 +010092
93 /*
Soby Mathewbc912822015-09-22 12:01:18 +010094 * Acknowledge and handle the secure timer interrupt. Also sanity check
95 * if it has been preempted by another interrupt through an assertion.
Achin Gupta76717892014-05-09 11:42:56 +010096 */
Dan Handley701fea72014-05-27 16:17:21 +010097 id = plat_ic_acknowledge_interrupt();
Dan Handley4fd2f5c2014-08-04 11:41:20 +010098 assert(id == TSP_IRQ_SEC_PHY_TIMER);
Achin Gupta76717892014-05-09 11:42:56 +010099 tsp_generic_timer_handler();
Dan Handley701fea72014-05-27 16:17:21 +0100100 plat_ic_end_of_interrupt(id);
Achin Gupta76717892014-05-09 11:42:56 +0100101
102 /* Update the statistics and print some messages */
Soby Mathewbec98512015-09-03 18:29:38 +0100103 tsp_stats[linear_id].sel1_intr_count++;
Dan Handley91b624e2014-07-29 17:14:00 +0100104#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
Achin Gupta76717892014-05-09 11:42:56 +0100105 spin_lock(&console_lock);
Soby Mathewbec98512015-09-03 18:29:38 +0100106 VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n",
Soby Mathewda43b662015-07-08 21:45:46 +0100107 read_mpidr(), id);
Soby Mathewbec98512015-09-03 18:29:38 +0100108 VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n",
109 read_mpidr(), tsp_stats[linear_id].sel1_intr_count);
Achin Gupta76717892014-05-09 11:42:56 +0100110 spin_unlock(&console_lock);
Dan Handley91b624e2014-07-29 17:14:00 +0100111#endif
Achin Gupta76717892014-05-09 11:42:56 +0100112 return 0;
113}