| Chandni Cherukuri | 626a52d | 2018-08-16 13:43:23 +0530 | [diff] [blame] | 1 | /* |
| Aditya Angadi | 7b424ba | 2019-12-31 10:14:32 +0530 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, Arm Limited. All rights reserved. |
| Chandni Cherukuri | 626a52d | 2018-08-16 13:43:23 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| 9 | |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| 11 | |
| Chandni Cherukuri | 626a52d | 2018-08-16 13:43:23 +0530 | [diff] [blame] | 12 | #include <sgi_base_platform_def.h> |
| Chandni Cherukuri | 626a52d | 2018-08-16 13:43:23 +0530 | [diff] [blame] | 13 | |
| Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 14 | #define PLAT_ARM_CLUSTER_COUNT U(2) |
| 15 | #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(8) |
| 16 | #define CSS_SGI_MAX_PE_PER_CPU U(2) |
| Chandni Cherukuri | 626a52d | 2018-08-16 13:43:23 +0530 | [diff] [blame] | 17 | |
| 18 | #define PLAT_CSS_MHU_BASE UL(0x45400000) |
| 19 | |
| 20 | /* Base address of DMC-620 instances */ |
| Chandni Cherukuri | 533b554 | 2019-02-22 16:44:49 +0530 | [diff] [blame] | 21 | #define RDE1EDGE_DMC620_BASE0 UL(0x4e000000) |
| 22 | #define RDE1EDGE_DMC620_BASE1 UL(0x4e100000) |
| Chandni Cherukuri | 626a52d | 2018-08-16 13:43:23 +0530 | [diff] [blame] | 23 | |
| 24 | #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 |
| 25 | |
| 26 | #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 |
| 27 | |
| Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 28 | /* |
| 29 | * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes |
| 30 | */ |
| Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 31 | #ifdef __aarch64__ |
| Manoj Kumar | 69bebd8 | 2019-06-21 17:07:13 +0100 | [diff] [blame] | 32 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) |
| 33 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) |
| 34 | #else |
| 35 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) |
| 36 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) |
| 37 | #endif |
| 38 | |
| Vijayenthiran Subramaniam | 64c9645 | 2020-02-03 12:14:01 +0530 | [diff] [blame] | 39 | /* GIC related constants */ |
| 40 | #define PLAT_ARM_GICD_BASE UL(0x30000000) |
| 41 | #define PLAT_ARM_GICC_BASE UL(0x2C000000) |
| 42 | #define PLAT_ARM_GICR_BASE UL(0x300C0000) |
| 43 | |
| Chandni Cherukuri | 626a52d | 2018-08-16 13:43:23 +0530 | [diff] [blame] | 44 | #endif /* PLATFORM_DEF_H */ |