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Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <bl_common.h>
34#include <cortex_a53.h>
35#include <cortex_a72.h>
36#include <plat_private.h>
37#include <platform_def.h>
Tony Xie42e113e2016-07-16 11:16:51 +080038#include <plat_pmu_macros.S>
Tony Xief6118cc2016-01-15 17:17:32 +080039
40 .globl cpuson_entry_point
41 .globl cpuson_flags
42 .globl platform_cpu_warmboot
43 .globl plat_secondary_cold_boot_setup
44 .globl plat_report_exception
45 .globl platform_is_primary_cpu
46 .globl plat_crash_console_init
47 .globl plat_crash_console_putc
48 .globl plat_my_core_pos
49 .globl plat_reset_handler
50
Tony Xief6118cc2016-01-15 17:17:32 +080051 /*
52 * void plat_reset_handler(void);
53 *
54 * Determine the SOC type and call the appropriate reset
55 * handler.
56 *
57 */
58func plat_reset_handler
Tony Xie42e113e2016-07-16 11:16:51 +080059 mrs x0, midr_el1
60 ubfx x0, x0, MIDR_PN_SHIFT, #12
61 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
62 b.eq handler_a72
63 b handler_end
64handler_a72:
65 /*
66 * This handler does the following:
67 * Set the L2 Data RAM latency for Cortex-A72.
68 * Set the L2 Tag RAM latency to for Cortex-A72.
69 */
70 mov x0, #((2 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
71 (0x1 << 5))
72 msr L2CTLR_EL1, x0
73 isb
74handler_end:
75 ret
Tony Xief6118cc2016-01-15 17:17:32 +080076endfunc plat_reset_handler
77
78func plat_my_core_pos
79 mrs x0, mpidr_el1
80 and x1, x0, #MPIDR_CPU_MASK
81 and x0, x0, #MPIDR_CLUSTER_MASK
Tony Xie42e113e2016-07-16 11:16:51 +080082 add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
Tony Xief6118cc2016-01-15 17:17:32 +080083 ret
84endfunc plat_my_core_pos
85
86 /* --------------------------------------------------------------------
87 * void plat_secondary_cold_boot_setup (void);
88 *
89 * This function performs any platform specific actions
90 * needed for a secondary cpu after a cold reset e.g
91 * mark the cpu's presence, mechanism to place it in a
92 * holding pen etc.
93 * --------------------------------------------------------------------
94 */
95func plat_secondary_cold_boot_setup
96 /* rk3368 does not do cold boot for secondary CPU */
97cb_panic:
98 b cb_panic
99endfunc plat_secondary_cold_boot_setup
100
101func platform_is_primary_cpu
102 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
103 cmp x0, #PLAT_RK_PRIMARY_CPU
104 cset x0, eq
105 ret
106endfunc platform_is_primary_cpu
107
108 /* --------------------------------------------------------------------
109 * int plat_crash_console_init(void)
110 * Function to initialize the crash console
111 * without a C Runtime to print crash report.
112 * Clobber list : x0, x1, x2
113 * --------------------------------------------------------------------
114 */
115func plat_crash_console_init
116 mov_imm x0, PLAT_RK_UART_BASE
117 mov_imm x1, PLAT_RK_UART_CLOCK
118 mov_imm x2, PLAT_RK_UART_BAUDRATE
119 b console_core_init
120endfunc plat_crash_console_init
121
122 /* --------------------------------------------------------------------
123 * int plat_crash_console_putc(void)
124 * Function to print a character on the crash
125 * console without a C Runtime.
126 * Clobber list : x1, x2
127 * --------------------------------------------------------------------
128 */
129func plat_crash_console_putc
130 mov_imm x1, PLAT_RK_UART_BASE
131 b console_core_putc
132endfunc plat_crash_console_putc
133
134 /* --------------------------------------------------------------------
135 * void platform_cpu_warmboot (void);
136 * cpus online or resume enterpoint
137 * --------------------------------------------------------------------
138 */
Caesar Wang59e41b52016-04-10 14:11:07 +0800139 .align 16
Tony Xief6118cc2016-01-15 17:17:32 +0800140func platform_cpu_warmboot
141 mrs x0, MPIDR_EL1
Tony Xie42e113e2016-07-16 11:16:51 +0800142 and x19, x0, #MPIDR_CPU_MASK
143 and x20, x0, #MPIDR_CLUSTER_MASK
144 mov x0, x20
145 func_rockchip_clst_warmboot
Tony Xief6118cc2016-01-15 17:17:32 +0800146 /* --------------------------------------------------------------------
147 * big cluster id is 1
148 * big cores id is from 0-3, little cores id 4-7
149 * --------------------------------------------------------------------
150 */
Tony Xie42e113e2016-07-16 11:16:51 +0800151 add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT
Tony Xief6118cc2016-01-15 17:17:32 +0800152 /* --------------------------------------------------------------------
153 * get per cpuup flag
154 * --------------------------------------------------------------------
155 */
156 adr x4, cpuson_flags
Tony Xie42e113e2016-07-16 11:16:51 +0800157 add x4, x4, x21, lsl #2
Tony Xief6118cc2016-01-15 17:17:32 +0800158 ldr w1, [x4]
159 /* --------------------------------------------------------------------
Tony Xief6118cc2016-01-15 17:17:32 +0800160 * check cpuon reason
161 * --------------------------------------------------------------------
162 */
Tony Xie42e113e2016-07-16 11:16:51 +0800163 cmp w1, PMU_CPU_AUTO_PWRDN
Tony Xief6118cc2016-01-15 17:17:32 +0800164 b.eq boot_entry
Tony Xie42e113e2016-07-16 11:16:51 +0800165 cmp w1, PMU_CPU_HOTPLUG
Tony Xief6118cc2016-01-15 17:17:32 +0800166 b.eq boot_entry
167 /* --------------------------------------------------------------------
168 * If the boot core cpuson_flags or cpuson_entry_point is not
169 * expection. force the core into wfe.
170 * --------------------------------------------------------------------
171 */
172wfe_loop:
173 wfe
174 b wfe_loop
175boot_entry:
Tony Xie42e113e2016-07-16 11:16:51 +0800176 str wzr, [x4]
Caesar Wang59e41b52016-04-10 14:11:07 +0800177 /* --------------------------------------------------------------------
178 * get per cpuup boot addr
179 * --------------------------------------------------------------------
180 */
181 adr x5, cpuson_entry_point
Tony Xie42e113e2016-07-16 11:16:51 +0800182 ldr x2, [x5, x21, lsl #3]
Tony Xief6118cc2016-01-15 17:17:32 +0800183 br x2
184endfunc platform_cpu_warmboot
185
186 /* --------------------------------------------------------------------
187 * Per-CPU Secure entry point - resume or power up
188 * --------------------------------------------------------------------
189 */
190 .section tzfw_coherent_mem, "a"
191 .align 3
192cpuson_entry_point:
193 .rept PLATFORM_CORE_COUNT
194 .quad 0
195 .endr
196cpuson_flags:
197 .rept PLATFORM_CORE_COUNT
Caesar Wang59e41b52016-04-10 14:11:07 +0800198 .word 0
Tony Xief6118cc2016-01-15 17:17:32 +0800199 .endr
Tony Xie42e113e2016-07-16 11:16:51 +0800200rockchip_clst_warmboot_data