| Deepak Pandey | 9cbacf6 | 2018-08-08 10:32:51 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <cortex_ares.h> |
| 10 | #include <cpu_macros.S> |
| 11 | #include <platform_def.h> |
| 12 | |
| 13 | .globl plat_arm_calc_core_pos |
| 14 | .globl plat_reset_handler |
| 15 | |
| 16 | /* ----------------------------------------------------- |
| 17 | * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) |
| 18 | * |
| 19 | * Helper function to calculate the core position. |
| 20 | * (ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER * N1SDP_MAX_PE_PER_CPU) + |
| 21 | * (CPUId * N1SDP_MAX_PE_PER_CPU) + |
| 22 | * ThreadId |
| 23 | * |
| 24 | * which can be simplified as: |
| 25 | * |
| 26 | * ((ClusterId * N1SDP_MAX_CPUS_PER_CLUSTER + CPUId) * |
| 27 | * N1SDP_MAX_PE_PER_CPU) + ThreadId |
| 28 | * ------------------------------------------------------ |
| 29 | */ |
| 30 | |
| 31 | func plat_arm_calc_core_pos |
| 32 | mov x3, x0 |
| 33 | |
| 34 | /* |
| 35 | * The MT bit in MPIDR is always set for n1sdp and the |
| 36 | * affinity level 0 corresponds to thread affinity level. |
| 37 | */ |
| 38 | |
| 39 | /* Extract individual affinity fields from MPIDR */ |
| 40 | ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS |
| 41 | ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS |
| 42 | ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS |
| 43 | |
| 44 | /* Compute linear position */ |
| 45 | mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER |
| 46 | madd x1, x2, x4, x1 |
| 47 | mov x5, #N1SDP_MAX_PE_PER_CPU |
| 48 | madd x0, x1, x5, x0 |
| 49 | ret |
| 50 | endfunc plat_arm_calc_core_pos |
| 51 | |
| 52 | /* ----------------------------------------------------- |
| 53 | * void plat_reset_handler(void); |
| 54 | * |
| 55 | * Determine the CPU MIDR and disable power down bit for |
| 56 | * that CPU. |
| 57 | * ----------------------------------------------------- |
| 58 | */ |
| 59 | |
| 60 | func plat_reset_handler |
| 61 | jump_if_cpu_midr CORTEX_ARES_MIDR, ARES |
| 62 | ret |
| 63 | |
| 64 | /* ----------------------------------------------------- |
| 65 | * Disable CPU power down bit in power control register |
| 66 | * ----------------------------------------------------- |
| 67 | */ |
| 68 | ARES: |
| 69 | mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 |
| 70 | bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK |
| 71 | msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 |
| 72 | isb |
| 73 | ret |
| 74 | endfunc plat_reset_handler |