Bharat Gooty | 29e3eb9 | 2020-09-24 15:29:28 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2019 - 2021, Broadcom |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <stdint.h> |
| 8 | |
| 9 | #include <common/debug.h> |
| 10 | #include <drivers/delay_timer.h> |
| 11 | #include <lib/mmio.h> |
| 12 | |
| 13 | #include <mdio.h> |
| 14 | #include <platform_usb.h> |
| 15 | #include <sr_utils.h> |
| 16 | #include "sr_usb.h" |
| 17 | #include <usbh_xhci_regs.h> |
| 18 | |
| 19 | static uint32_t usb_func = USB3_DRD | USB3H_USB2DRD; |
| 20 | |
| 21 | static void usb_pm_rescal_init(void) |
| 22 | { |
| 23 | uint32_t data; |
| 24 | uint32_t try; |
| 25 | |
| 26 | mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_PM_RESET_N_R); |
| 27 | /* release reset */ |
| 28 | mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0, RESCAL_I_RSTB); |
| 29 | udelay(10U); |
| 30 | /* power up */ |
| 31 | mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0, |
| 32 | RESCAL_I_RSTB | RESCAL_I_PWRDNB); |
| 33 | try = 1000U; |
| 34 | do { |
| 35 | udelay(1U); |
| 36 | data = mmio_read_32(CDRU_CHIP_TOP_SPARE_REG1); |
| 37 | try--; |
| 38 | } while ((data & RESCAL_I_PWRDNB) == 0x0U && (try != 0U)); |
| 39 | |
| 40 | if (try == 0U) { |
| 41 | ERROR("CDRU_CHIP_TOP_SPARE_REG1: 0x%x\n", data); |
| 42 | } |
| 43 | |
| 44 | INFO("USB and PM Rescal Init done..\n"); |
| 45 | } |
| 46 | |
| 47 | const unsigned int xhc_portsc_reg_offset[MAX_USB_PORTS] = { |
| 48 | XHC_PORTSC1_OFFSET, |
| 49 | XHC_PORTSC2_OFFSET, |
| 50 | XHC_PORTSC3_OFFSET, |
| 51 | }; |
| 52 | |
| 53 | static void usb3h_usb2drd_init(void) |
| 54 | { |
| 55 | uint32_t val; |
| 56 | |
| 57 | INFO("USB3H + USB 2DRD init\n"); |
| 58 | mmio_clrbits_32(USB3H_U3PHY_CTRL, POR_RESET); |
| 59 | val = mmio_read_32(USB3H_PWR_CTRL); |
| 60 | val &= ~(0x3U << POWER_CTRL_OVRD); |
| 61 | val |= (1U << POWER_CTRL_OVRD); |
| 62 | mmio_write_32(USB3H_PWR_CTRL, val); |
| 63 | mmio_setbits_32(USB3H_U3PHY_CTRL, PHY_RESET); |
| 64 | /* Phy to come out of reset */ |
| 65 | udelay(2U); |
| 66 | mmio_clrbits_32(USB3H_U3PHY_CTRL, MDIO_RESET); |
| 67 | |
| 68 | /* MDIO in reset */ |
| 69 | udelay(2U); |
| 70 | mmio_setbits_32(USB3H_U3PHY_CTRL, MDIO_RESET); |
| 71 | |
| 72 | /* After MDIO reset release */ |
| 73 | udelay(2U); |
| 74 | |
| 75 | /* USB 3.0 phy Analog Block Initialization */ |
| 76 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG, |
| 77 | USB3_PHY_ANA_BLOCK_BASE); |
| 78 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG0, 0x4646U); |
| 79 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG1, 0x80c9U); |
| 80 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG2, 0x88a6U); |
| 81 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG5, 0x7c12U); |
| 82 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG8, 0x1d07U); |
| 83 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG11, 0x25cU); |
| 84 | |
| 85 | /* USB 3.0 phy RXPMD Block initialization*/ |
| 86 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG, |
| 87 | USB3_PHY_RXPMD_BLOCK_BASE); |
| 88 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG1, 0x4052U); |
| 89 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG2, 0x4cU); |
| 90 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG5, 0x7U); |
| 91 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG7, 0x173U); |
| 92 | |
| 93 | /* USB 3.0 phy AEQ Block initialization*/ |
| 94 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG, |
| 95 | USB3_PHY_AEQ_BLOCK_BASE); |
| 96 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_AEQ_REG1, 0x3000U); |
| 97 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_AEQ_REG3, 0x2c70U); |
| 98 | |
| 99 | /* USB 3.0 phy TXPMD Block initialization*/ |
| 100 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG, |
| 101 | USB3_PHY_TXPMD_BLOCK_BASE); |
| 102 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_TXPMD_REG1, 0x100fU); |
| 103 | mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_TXPMD_REG2, 0x238cU); |
| 104 | } |
| 105 | |
| 106 | static void usb3drd_init(void) |
| 107 | { |
| 108 | uint32_t val; |
| 109 | |
| 110 | INFO("USB3DRD init\n"); |
| 111 | mmio_clrbits_32(DRDU3_U3PHY_CTRL, POR_RESET); |
| 112 | val = mmio_read_32(DRDU3_PWR_CTRL); |
| 113 | val &= ~(0x3U << POWER_CTRL_OVRD); |
| 114 | val |= (1U << POWER_CTRL_OVRD); |
| 115 | mmio_write_32(DRDU3_PWR_CTRL, val); |
| 116 | mmio_setbits_32(DRDU3_U3PHY_CTRL, PHY_RESET); |
| 117 | /* Phy to come out of reset */ |
| 118 | udelay(2U); |
| 119 | mmio_clrbits_32(DRDU3_U3PHY_CTRL, MDIO_RESET); |
| 120 | |
| 121 | /* MDIO in reset */ |
| 122 | udelay(2U); |
| 123 | mmio_setbits_32(DRDU3_U3PHY_CTRL, MDIO_RESET); |
| 124 | |
| 125 | /* After MDIO reset release */ |
| 126 | udelay(2U); |
| 127 | |
| 128 | /* USB 3.0 DRD phy Analog Block Initialization */ |
| 129 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG, |
| 130 | USB3_PHY_ANA_BLOCK_BASE); |
| 131 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG0, 0x4646U); |
| 132 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG1, 0x80c9U); |
| 133 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG2, 0x88a6U); |
| 134 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG5, 0x7c12U); |
| 135 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG8, 0x1d07U); |
| 136 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG11, 0x25cU); |
| 137 | |
| 138 | /* USB 3.0 DRD phy RXPMD Block initialization*/ |
| 139 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG, |
| 140 | USB3_PHY_RXPMD_BLOCK_BASE); |
| 141 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG1, 0x4052U); |
| 142 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG2, 0x4cU); |
| 143 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG5, 0x7U); |
| 144 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG7, 0x173U); |
| 145 | |
| 146 | /* USB 3.0 DRD phy AEQ Block initialization*/ |
| 147 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG, |
| 148 | USB3_PHY_AEQ_BLOCK_BASE); |
| 149 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_AEQ_REG1, 0x3000U); |
| 150 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_AEQ_REG3, 0x2c70U); |
| 151 | |
| 152 | /* USB 3.0 DRD phy TXPMD Block initialization*/ |
| 153 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG, |
| 154 | USB3_PHY_TXPMD_BLOCK_BASE); |
| 155 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_TXPMD_REG1, 0x100fU); |
| 156 | mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_TXPMD_REG2, 0x238cU); |
| 157 | } |
| 158 | |
| 159 | static void usb3_phy_init(void) |
| 160 | { |
| 161 | usb_pm_rescal_init(); |
| 162 | |
| 163 | if ((usb_func & USB3H_USB2DRD) != 0U) { |
| 164 | usb3h_usb2drd_init(); |
| 165 | } |
| 166 | |
| 167 | if ((usb_func & USB3_DRD) != 0U) { |
| 168 | usb3drd_init(); |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | #ifdef USB_DMA_COHERENT |
| 173 | void usb_enable_coherence(void) |
| 174 | { |
| 175 | if (usb_func & USB3H_USB2DRD) { |
| 176 | mmio_setbits_32(USB3H_SOFT_RESET_CTRL, |
| 177 | USB3H_XHC_AXI_SOFT_RST_N); |
| 178 | mmio_setbits_32(DRDU2_SOFT_RESET_CTRL, |
| 179 | DRDU2_BDC_AXI_SOFT_RST_N); |
| 180 | mmio_setbits_32(USB3H_U3PHY_CTRL, USB3H_U3SOFT_RST_N); |
| 181 | mmio_setbits_32(DRDU2_PHY_CTRL, DRDU2_U2SOFT_RST_N); |
| 182 | |
| 183 | mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIWRA, |
| 184 | (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK), |
| 185 | (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL)); |
| 186 | |
| 187 | mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIRDA, |
| 188 | (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK), |
| 189 | (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL)); |
| 190 | |
| 191 | mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIWRA, |
| 192 | (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK), |
| 193 | (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL)); |
| 194 | |
| 195 | mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIRDA, |
| 196 | (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK), |
| 197 | (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL)); |
| 198 | |
| 199 | } |
| 200 | |
| 201 | if (usb_func & USB3_DRD) { |
| 202 | mmio_setbits_32(DRDU3_SOFT_RESET_CTRL, |
| 203 | (DRDU3_XHC_AXI_SOFT_RST_N | |
| 204 | DRDU3_BDC_AXI_SOFT_RST_N)); |
| 205 | mmio_setbits_32(DRDU3_U3PHY_CTRL, |
| 206 | (DRDU3_U3XHC_SOFT_RST_N | |
| 207 | DRDU3_U3BDC_SOFT_RST_N)); |
| 208 | |
| 209 | mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIWRA, |
| 210 | (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK), |
| 211 | (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL)); |
| 212 | |
| 213 | mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIRDA, |
| 214 | (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK), |
| 215 | (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL)); |
| 216 | |
| 217 | mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIWRA, |
| 218 | (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK), |
| 219 | (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL)); |
| 220 | |
| 221 | mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIRDA, |
| 222 | (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK), |
| 223 | (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL)); |
| 224 | } |
| 225 | } |
| 226 | #endif |
| 227 | |
| 228 | void xhci_phy_init(void) |
| 229 | { |
| 230 | uint32_t val; |
| 231 | |
| 232 | INFO("usb init start\n"); |
| 233 | mmio_setbits_32(CDRU_MISC_CLK_ENABLE_CONTROL, |
| 234 | CDRU_MISC_CLK_USBSS); |
| 235 | |
| 236 | mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_USBSS_RESET_N); |
| 237 | |
| 238 | if (usb_func & USB3_DRD) { |
| 239 | VERBOSE(" - configure stream_id = 0x6800 for DRDU3\n"); |
| 240 | val = SR_SID_VAL(0x3U, 0x1U, 0x0U) << ICFG_USB_SID_SHIFT; |
| 241 | mmio_write_32(ICFG_DRDU3_SID_CTRL + ICFG_USB_SID_AWADDR_OFFSET, |
| 242 | val); |
| 243 | mmio_write_32(ICFG_DRDU3_SID_CTRL + ICFG_USB_SID_ARADDR_OFFSET, |
| 244 | val); |
| 245 | |
| 246 | /* |
| 247 | * DRDU3 Device USB Space, DRDU3 Host USB Space, |
| 248 | * DRDU3 SS Config |
| 249 | */ |
| 250 | mmio_setbits_32(USBIC_GPV_SECURITY10, |
| 251 | USBIC_GPV_SECURITY10_FIELD); |
| 252 | } |
| 253 | |
| 254 | if (usb_func & USB3H_USB2DRD) { |
| 255 | VERBOSE(" - configure stream_id = 0x6801 for USB3H\n"); |
| 256 | val = SR_SID_VAL(0x3U, 0x1U, 0x1U) << ICFG_USB_SID_SHIFT; |
| 257 | mmio_write_32(ICFG_USB3H_SID_CTRL + ICFG_USB_SID_AWADDR_OFFSET, |
| 258 | val); |
| 259 | mmio_write_32(ICFG_USB3H_SID_CTRL + ICFG_USB_SID_ARADDR_OFFSET, |
| 260 | val); |
| 261 | |
| 262 | VERBOSE(" - configure stream_id = 0x6802 for DRDU2\n"); |
| 263 | val = SR_SID_VAL(0x3U, 0x1U, 0x2U) << ICFG_USB_SID_SHIFT; |
| 264 | mmio_write_32(ICFG_DRDU2_SID_CTRL + ICFG_USB_SID_AWADDR_OFFSET, |
| 265 | val); |
| 266 | mmio_write_32(ICFG_DRDU2_SID_CTRL + ICFG_USB_SID_ARADDR_OFFSET, |
| 267 | val); |
| 268 | |
| 269 | /* DRDU2 APB Bridge:DRDU2 USB Device, USB3H SS Config */ |
| 270 | mmio_setbits_32(USBIC_GPV_SECURITY1, USBIC_GPV_SECURITY1_FIELD); |
| 271 | |
| 272 | /* |
| 273 | * USB3H APB Bridge:DRDU2 Host + USB3 Host USB Space, |
| 274 | * USB3H SS Config |
| 275 | */ |
| 276 | mmio_setbits_32(USBIC_GPV_SECURITY2, USBIC_GPV_SECURITY2_FIELD); |
| 277 | } |
| 278 | |
| 279 | /* Configure Host masters as non-Secure */ |
| 280 | mmio_setbits_32(USBSS_TZPCDECPROT0set, USBSS_TZPCDECPROT0); |
| 281 | |
| 282 | /* CCN Slave on USBIC */ |
| 283 | mmio_setbits_32(USBIC_GPV_SECURITY0, USBIC_GPV_SECURITY0_FIELD); |
| 284 | |
| 285 | /* SLAVE_8:IDM Register Space */ |
| 286 | mmio_setbits_32(USBIC_GPV_SECURITY4, USBIC_GPV_SECURITY4_FIELD); |
| 287 | |
| 288 | usb3_phy_init(); |
| 289 | #ifdef USB_DMA_COHERENT |
| 290 | usb_enable_coherence(); |
| 291 | #endif |
| 292 | |
| 293 | usb_device_init(usb_func); |
| 294 | |
| 295 | INFO("PLAT USB: init done.\n"); |
| 296 | } |