| Joel Hutton | a7c4687 | 2018-01-10 16:06:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __CORTEX_HELIOS_H__ |
| 8 | #define __CORTEX_HELIOS_H__ |
| 9 | |
| 10 | #define CORTEX_HELIOS_MIDR U(0x410FD060) |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * CPU Extended Control register specific definitions. |
| 14 | ******************************************************************************/ |
| 15 | #define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 |
| 16 | |
| 17 | /******************************************************************************* |
| 18 | * CPU Auxiliary Control register specific definitions. |
| 19 | ******************************************************************************/ |
| 20 | #define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 |
| 21 | |
| 22 | /******************************************************************************* |
| 23 | * CPU Power Control register specific definitions. |
| 24 | ******************************************************************************/ |
| 25 | |
| 26 | #define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 27 | #define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) |
| 28 | |
| 29 | #endif /* __CORTEX_HELIOS_H__ */ |