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Konstantin Porotchkinf69ec582018-06-07 18:31:14 +03001/*
2 * Copyright (C) 2017 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7#ifndef _ARO_H_
8#define _ARO_H_
9
10enum hws_freq {
11 CPU_FREQ_2000,
12 CPU_FREQ_1800,
13 CPU_FREQ_1600,
14 CPU_FREQ_1400,
15 CPU_FREQ_1300,
16 CPU_FREQ_1200,
17 CPU_FREQ_1000,
18 CPU_FREQ_600,
19 CPU_FREQ_800,
20 DDR_FREQ_LAST,
21 DDR_FREQ_SAR
22};
23
24enum cpu_clock_freq_mode {
25 CPU_2000_DDR_1200_RCLK_1200 = 0x0,
26 CPU_2000_DDR_1050_RCLK_1050 = 0x1,
27 CPU_1600_DDR_800_RCLK_800 = 0x4,
28 CPU_1800_DDR_1200_RCLK_1200 = 0x6,
29 CPU_1800_DDR_1050_RCLK_1050 = 0x7,
30 CPU_1600_DDR_900_RCLK_900 = 0x0B,
31 CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
Christine Gharzuzi46a4fc62018-08-02 20:25:11 +030032 CPU_1600_DDR_1200_RCLK_1200 = 0x0D,
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +030033 CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
34 CPU_1000_DDR_650_RCLK_650 = 0x13,
35 CPU_1300_DDR_800_RCLK_800 = 0x14,
36 CPU_1300_DDR_650_RCLK_650 = 0x17,
37 CPU_1200_DDR_800_RCLK_800 = 0x19,
38 CPU_1400_DDR_800_RCLK_800 = 0x1a,
39 CPU_600_DDR_800_RCLK_800 = 0x1B,
40 CPU_800_DDR_800_RCLK_800 = 0x1C,
41 CPU_1000_DDR_800_RCLK_800 = 0x1D,
42 CPU_DDR_RCLK_INVALID
43};
44
45int init_aro(void);
46
47#endif /* _ARO_H_ */