blob: 42f865349566547ca8830d6823fcb05eafcba817 [file] [log] [blame]
Jorge Ramirez-Ortiz7c21e1c2018-09-23 09:42:08 +02001/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/debug.h>
9#include <drivers/arm/gicv2.h>
10#include <lib/mmio.h>
11
Jorge Ramirez-Ortiz7c21e1c2018-09-23 09:42:08 +020012#include "rcar_def.h"
13
14extern void gicd_set_icenabler(uintptr_t base, unsigned int id);
15
16#define RST_BASE (0xE6160000U)
17#define RST_WDTRSTCR (RST_BASE + 0x0054U)
18#define SWDT_BASE (0xE6030000U)
19#define SWDT_WTCNT (SWDT_BASE + 0x0000U)
20#define SWDT_WTCSRA (SWDT_BASE + 0x0004U)
21#define SWDT_WTCSRB (SWDT_BASE + 0x0008U)
22#define SWDT_GICD_BASE (0xF1010000U)
23#define SWDT_GICC_BASE (0xF1020000U)
24#define SWDT_GICD_CTLR (SWDT_GICD_BASE + 0x0000U)
25#define SWDT_GICD_IGROUPR (SWDT_GICD_BASE + 0x0080U)
26#define SWDT_GICD_ISPRIORITYR (SWDT_GICD_BASE + 0x0400U)
27#define SWDT_GICC_CTLR (SWDT_GICC_BASE + 0x0000U)
28#define SWDT_GICC_PMR (SWDT_GICC_BASE + 0x0004U)
29#define SWDT_GICD_ITARGETSR (SWDT_GICD_BASE + 0x0800U)
30#define IGROUPR_NUM (16U)
31#define ISPRIORITY_NUM (128U)
32#define ITARGET_MASK (0x03U)
33
34#define WDTRSTCR_UPPER_BYTE (0xA55A0000U)
35#define WTCSRA_UPPER_BYTE (0xA5A5A500U)
36#define WTCSRB_UPPER_BYTE (0xA5A5A500U)
37#define WTCNT_UPPER_BYTE (0x5A5A0000U)
38#define WTCNT_RESET_VALUE (0xF488U)
39#define WTCSRA_BIT_CKS (0x0007U)
40#define WTCSRB_BIT_CKS (0x003FU)
41#define SWDT_RSTMSK (1U << 1U)
42#define WTCSRA_WOVFE (1U << 3U)
43#define WTCSRA_WRFLG (1U << 5U)
44#define SWDT_ENABLE (1U << 7U)
45
46#define WDTRSTCR_MASK_ALL (0x0000FFFFU)
47#define WTCSRA_MASK_ALL (0x000000FFU)
48#define WTCNT_INIT_DATA (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE)
49#define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU)
50#define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U)
51
52#define WTCNT_COUNT_8p13k (0x10000U - 40687U)
53#define WTCNT_COUNT_8p13k_H3VER10 (0x10000U - 20343U)
54#define WTCNT_COUNT_8p22k (0x10000U - 41115U)
55#define WTCNT_COUNT_7p81k (0x10000U - 39062U)
56#define WTCSRA_CKS_DIV16 (0x00000002U)
57
58static void swdt_disable(void)
59{
60 uint32_t rmsk;
61
62 rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL;
63 rmsk |= SWDT_RSTMSK;
64 mmio_write_32(RST_WDTRSTCR, WDTRSTCR_UPPER_BYTE | rmsk);
65
66 mmio_write_32(SWDT_WTCNT, WTCNT_INIT_DATA);
67 mmio_write_32(SWDT_WTCSRA, WTCSRA_INIT_DATA);
68 mmio_write_32(SWDT_WTCSRB, WTCSRB_INIT_DATA);
69
70 /* Set the interrupt clear enable register */
71 gicd_set_icenabler(RCAR_GICD_BASE, ARM_IRQ_SEC_WDT);
72}
73
74void rcar_swdt_init(void)
75{
ldts0a596b42018-11-06 10:17:12 +010076 uint32_t rmsk, sr;
Jorge Ramirez-Ortiz7c21e1c2018-09-23 09:42:08 +020077#if (RCAR_LSI != RCAR_E3)
ldts0a596b42018-11-06 10:17:12 +010078 uint32_t reg, val, product_cut, chk_data;
Jorge Ramirez-Ortiz7c21e1c2018-09-23 09:42:08 +020079
80 reg = mmio_read_32(RCAR_PRR);
81 product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
82
83 reg = mmio_read_32(RCAR_MODEMR);
84 chk_data = reg & CHECK_MD13_MD14;
85#endif
86 /* stop watchdog */
87 if (mmio_read_32(SWDT_WTCSRA) & SWDT_ENABLE)
88 mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE);
89
90 mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE |
91 WTCSRA_WOVFE | WTCSRA_CKS_DIV16);
92
93#if (RCAR_LSI == RCAR_E3)
94 mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k);
95#else
96 val = WTCNT_UPPER_BYTE;
97
98 switch (chk_data) {
99 case MD14_MD13_TYPE_0:
100 case MD14_MD13_TYPE_2:
101 val |= WTCNT_COUNT_8p13k;
102 break;
103 case MD14_MD13_TYPE_1:
104 val |= WTCNT_COUNT_8p22k;
105 break;
106 case MD14_MD13_TYPE_3:
107 val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ?
108 WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k;
109 break;
110 default:
111 ERROR("MODEMR ERROR value = %x\n", chk_data);
112 panic();
113 break;
114 }
115
116 mmio_write_32(SWDT_WTCNT, val);
117#endif
118 rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL;
119 rmsk |= SWDT_RSTMSK | WDTRSTCR_UPPER_BYTE;
120 mmio_write_32(RST_WDTRSTCR, rmsk);
121
122 while ((mmio_read_8(SWDT_WTCSRA) & WTCSRA_WRFLG) != 0U)
123 ;
124
125 /* Start the System WatchDog Timer */
126 sr = mmio_read_32(SWDT_WTCSRA) & WTCSRA_MASK_ALL;
127 mmio_write_32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | SWDT_ENABLE));
128}
129
130void rcar_swdt_release(void)
131{
132 uintptr_t itarget = SWDT_GICD_ITARGETSR +
133 (ARM_IRQ_SEC_WDT & ~ITARGET_MASK);
134 uint32_t i;
135
136 write_daifset(DAIF_FIQ_BIT);
137 swdt_disable();
138 gicv2_cpuif_disable();
139
140 for (i = 0; i < IGROUPR_NUM; i++)
141 mmio_write_32(SWDT_GICD_IGROUPR + i * 4, 0U);
142
143 for (i = 0; i < ISPRIORITY_NUM; i++)
144 mmio_write_32(SWDT_GICD_ISPRIORITYR + i * 4, 0U);
145
146 mmio_write_32(itarget, 0U);
147 mmio_write_32(SWDT_GICD_CTLR, 0U);
148 mmio_write_32(SWDT_GICC_CTLR, 0U);
149 mmio_write_32(SWDT_GICC_PMR, 0U);
150}
151
152void rcar_swdt_exec(uint64_t p)
153{
154 gicv2_end_of_interrupt(ARM_IRQ_SEC_WDT);
155 rcar_swdt_release();
156 ERROR("\n");
157 ERROR("System WDT overflow, occured address is %p\n", (void *)p);
158 panic();
159}