blob: 0fa6c73c9ab96e383239894578d387c73be4caa2 [file] [log] [blame]
Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Patrick Delaunay67bcec82022-02-16 15:45:44 +01002 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Julius Werner53456fc2019-07-09 13:49:11 -070017#ifndef __ASSEMBLER__
Yann Gautier091eab52019-06-04 18:06:34 +020018#include <drivers/st/bsec.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010019#include <drivers/st/stm32mp1_clk.h>
20
Yann Gautier57e282b2019-01-07 11:17:24 +010021#include <boot_api.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010022#include <stm32mp_common.h>
23#include <stm32mp_dt.h>
Yann Gautierc7374052019-06-04 18:02:37 +020024#include <stm32mp1_dbgmcu.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010025#include <stm32mp1_private.h>
Etienne Carriere316d6342019-12-02 10:08:48 +010026#include <stm32mp1_shared_resources.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010027#endif
28
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020029#include "stm32mp1_fip_def.h"
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020030
Yann Gautier4b0c72a2018-07-16 10:54:09 +020031/*******************************************************************************
Yann Gautierc7374052019-06-04 18:02:37 +020032 * CHIP ID
33 ******************************************************************************/
Yann Gautier16188f32020-02-12 15:38:34 +010034#if STM32MP13
35#define STM32MP1_CHIP_ID U(0x501)
36
37#define STM32MP135C_PART_NB U(0x05010000)
38#define STM32MP135A_PART_NB U(0x05010001)
39#define STM32MP133C_PART_NB U(0x050100C0)
40#define STM32MP133A_PART_NB U(0x050100C1)
41#define STM32MP131C_PART_NB U(0x050106C8)
42#define STM32MP131A_PART_NB U(0x050106C9)
43#define STM32MP135F_PART_NB U(0x05010800)
44#define STM32MP135D_PART_NB U(0x05010801)
45#define STM32MP133F_PART_NB U(0x050108C0)
46#define STM32MP133D_PART_NB U(0x050108C1)
47#define STM32MP131F_PART_NB U(0x05010EC8)
48#define STM32MP131D_PART_NB U(0x05010EC9)
49#endif
50#if STM32MP15
Yann Gautiera0a6ff62021-05-10 16:05:18 +020051#define STM32MP1_CHIP_ID U(0x500)
52
Yann Gautierc7374052019-06-04 18:02:37 +020053#define STM32MP157C_PART_NB U(0x05000000)
54#define STM32MP157A_PART_NB U(0x05000001)
55#define STM32MP153C_PART_NB U(0x05000024)
56#define STM32MP153A_PART_NB U(0x05000025)
57#define STM32MP151C_PART_NB U(0x0500002E)
58#define STM32MP151A_PART_NB U(0x0500002F)
Lionel Debieve7b64e3e2019-05-17 16:01:18 +020059#define STM32MP157F_PART_NB U(0x05000080)
60#define STM32MP157D_PART_NB U(0x05000081)
61#define STM32MP153F_PART_NB U(0x050000A4)
62#define STM32MP153D_PART_NB U(0x050000A5)
63#define STM32MP151F_PART_NB U(0x050000AE)
64#define STM32MP151D_PART_NB U(0x050000AF)
Yann Gautier16188f32020-02-12 15:38:34 +010065#endif
Yann Gautierc7374052019-06-04 18:02:37 +020066
67#define STM32MP1_REV_B U(0x2000)
Yann Gautier0fd6e232021-08-25 14:40:12 +020068#if STM32MP13
Yann Gautier06cc7912022-05-09 17:01:11 +020069#define STM32MP1_REV_Y U(0x1003)
Yann Gautier0fd6e232021-08-25 14:40:12 +020070#define STM32MP1_REV_Z U(0x1001)
71#endif
72#if STM32MP15
Lionel Debieve2d64b532019-06-25 10:40:37 +020073#define STM32MP1_REV_Z U(0x2001)
Yann Gautier0fd6e232021-08-25 14:40:12 +020074#endif
Yann Gautierc7374052019-06-04 18:02:37 +020075
76/*******************************************************************************
77 * PACKAGE ID
78 ******************************************************************************/
Yann Gautier16188f32020-02-12 15:38:34 +010079#if STM32MP15
Yann Gautierc7374052019-06-04 18:02:37 +020080#define PKG_AA_LFBGA448 U(4)
81#define PKG_AB_LFBGA354 U(3)
82#define PKG_AC_TFBGA361 U(2)
83#define PKG_AD_TFBGA257 U(1)
Yann Gautier16188f32020-02-12 15:38:34 +010084#endif
Yann Gautierc7374052019-06-04 18:02:37 +020085
86/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +020087 * STM32MP1 memory map related constants
88 ******************************************************************************/
Lionel Debieve7bd96f42019-09-03 12:22:23 +020089#define STM32MP_ROM_BASE U(0x00000000)
90#define STM32MP_ROM_SIZE U(0x00020000)
Yann Gautier3c93a252021-09-15 15:12:57 +020091#define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020092
Yann Gautier15e84832020-02-03 17:48:07 +010093#if STM32MP13
94#define STM32MP_SYSRAM_BASE U(0x2FFE0000)
95#define STM32MP_SYSRAM_SIZE U(0x00020000)
96#define SRAM1_BASE U(0x30000000)
97#define SRAM1_SIZE U(0x00004000)
98#define SRAM2_BASE U(0x30004000)
99#define SRAM2_SIZE U(0x00002000)
100#define SRAM3_BASE U(0x30006000)
101#define SRAM3_SIZE U(0x00002000)
Yann Gautier84d994b2020-04-14 18:08:50 +0200102#define SRAMS_BASE SRAM1_BASE
103#define SRAMS_SIZE_2MB_ALIGNED U(0x00200000)
Yann Gautier15e84832020-02-03 17:48:07 +0100104#endif /* STM32MP13 */
105#if STM32MP15
Yann Gautiera2e2a302019-02-14 11:13:39 +0100106#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
107#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier15e84832020-02-03 17:48:07 +0100108#endif /* STM32MP15 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200109
Etienne Carriere72369b12019-12-08 08:17:56 +0100110#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
111#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
112 STM32MP_SYSRAM_SIZE - \
113 STM32MP_NS_SYSRAM_SIZE)
114
Etienne Carriere34f0e932020-07-16 17:36:18 +0200115#define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
116#define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
117
Etienne Carriere72369b12019-12-08 08:17:56 +0100118#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
119#define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
120 STM32MP_NS_SYSRAM_SIZE)
121
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200122/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100123#define STM32MP_DDR_BASE U(0xC0000000)
124#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200125
126/* DDR power initializations */
Julius Werner53456fc2019-07-09 13:49:11 -0700127#ifndef __ASSEMBLER__
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200128enum ddr_type {
129 STM32MP_DDR3,
130 STM32MP_LPDDR2,
Yann Gautier917a00c2019-04-16 16:20:58 +0200131 STM32MP_LPDDR3
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200132};
133#endif
134
135/* Section used inside TF binaries */
Yann Gautier84d994b2020-04-14 18:08:50 +0200136#if STM32MP13
137/* 512 Octets reserved for header */
138#define STM32MP_HEADER_RESERVED_SIZE U(0x200)
139
140#define STM32MP_BINARY_BASE STM32MP_SEC_SYSRAM_BASE
141
142#define STM32MP_BINARY_SIZE STM32MP_SEC_SYSRAM_SIZE
143#endif
144#if STM32MP15
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200145#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200146/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100147#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautiera1ee9ed2020-09-17 11:30:18 +0200148/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
149#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200150
Etienne Carriere72369b12019-12-08 08:17:56 +0100151#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100152 STM32MP_PARAM_LOAD_SIZE + \
153 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200154
Etienne Carriere72369b12019-12-08 08:17:56 +0100155#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100156 (STM32MP_PARAM_LOAD_SIZE + \
157 STM32MP_HEADER_SIZE))
Yann Gautier84d994b2020-04-14 18:08:50 +0200158#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200159
Yann Gautierebc765f2020-01-16 18:50:51 +0100160/* BL2 and BL32/sp_min require finer granularity tables */
161#if defined(IMAGE_BL2)
162#define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
163#endif
164
165#if defined(IMAGE_BL32)
166#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
167#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200168
169/*
170 * MAX_MMAP_REGIONS is usually:
171 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
172 */
Yann Gautier9d135e42018-07-16 19:36:06 +0200173#if defined(IMAGE_BL2)
Yann Gautierebc765f2020-01-16 18:50:51 +0100174 #if STM32MP_USB_PROGRAMMER
175 #define MAX_MMAP_REGIONS 8
176 #else
177 #define MAX_MMAP_REGIONS 7
178 #endif
Yann Gautier9d135e42018-07-16 19:36:06 +0200179#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200180
Patrick Delaunay8bed83d2021-04-13 14:44:48 +0200181#if STM32MP13
182#define STM32MP_BL33_BASE STM32MP_DDR_BASE
183#endif
184#if STM32MP15
Yann Gautiera2e2a302019-02-14 11:13:39 +0100185#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Patrick Delaunay8bed83d2021-04-13 14:44:48 +0200186#endif
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200187#define STM32MP_BL33_MAX_SIZE U(0x400000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200188
Lionel Debieve402a46b2019-11-04 12:28:15 +0100189/* Define maximum page size for NAND devices */
190#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
191
Lionel Debieve129f6512021-04-13 17:11:00 +0200192/* Define location for the MTD scratch buffer */
193#if STM32MP13
194#define STM32MP_MTD_BUFFER (SRAM1_BASE + \
195 SRAM1_SIZE - \
196 PLATFORM_MTD_MAX_PAGE_SIZE)
197#endif
Yann Gautierc77afcb2023-08-31 12:58:35 +0200198
Lionel Debieve402a46b2019-11-04 12:28:15 +0100199/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200200 * STM32MP1 device/io map related constants (used for MMU)
201 ******************************************************************************/
202#define STM32MP1_DEVICE1_BASE U(0x40000000)
203#define STM32MP1_DEVICE1_SIZE U(0x40000000)
204
205#define STM32MP1_DEVICE2_BASE U(0x80000000)
206#define STM32MP1_DEVICE2_SIZE U(0x40000000)
207
208/*******************************************************************************
209 * STM32MP1 RCC
210 ******************************************************************************/
211#define RCC_BASE U(0x50000000)
212
213/*******************************************************************************
214 * STM32MP1 PWR
215 ******************************************************************************/
216#define PWR_BASE U(0x50001000)
217
218/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100219 * STM32MP1 GPIO
220 ******************************************************************************/
221#define GPIOA_BASE U(0x50002000)
222#define GPIOB_BASE U(0x50003000)
223#define GPIOC_BASE U(0x50004000)
224#define GPIOD_BASE U(0x50005000)
225#define GPIOE_BASE U(0x50006000)
226#define GPIOF_BASE U(0x50007000)
227#define GPIOG_BASE U(0x50008000)
228#define GPIOH_BASE U(0x50009000)
229#define GPIOI_BASE U(0x5000A000)
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100230#if STM32MP15
Yann Gautier038bff22019-01-17 19:17:47 +0100231#define GPIOJ_BASE U(0x5000B000)
232#define GPIOK_BASE U(0x5000C000)
233#define GPIOZ_BASE U(0x54004000)
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100234#endif
Yann Gautier038bff22019-01-17 19:17:47 +0100235#define GPIO_BANK_OFFSET U(0x1000)
236
237/* Bank IDs used in GPIO driver API */
238#define GPIO_BANK_A U(0)
239#define GPIO_BANK_B U(1)
240#define GPIO_BANK_C U(2)
241#define GPIO_BANK_D U(3)
242#define GPIO_BANK_E U(4)
243#define GPIO_BANK_F U(5)
244#define GPIO_BANK_G U(6)
245#define GPIO_BANK_H U(7)
246#define GPIO_BANK_I U(8)
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100247#if STM32MP15
Yann Gautier038bff22019-01-17 19:17:47 +0100248#define GPIO_BANK_J U(9)
249#define GPIO_BANK_K U(10)
250#define GPIO_BANK_Z U(25)
251
252#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
Yann Gautiercc5f89a2020-02-12 09:36:23 +0100253#endif
Yann Gautier038bff22019-01-17 19:17:47 +0100254
255/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200256 * STM32MP1 UART
257 ******************************************************************************/
Yann Gautierd476c772022-07-05 13:29:13 +0200258#if STM32MP13
259#define USART1_BASE U(0x4C000000)
260#define USART2_BASE U(0x4C001000)
261#endif
262#if STM32MP15
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200263#define USART1_BASE U(0x5C000000)
264#define USART2_BASE U(0x4000E000)
Yann Gautierd476c772022-07-05 13:29:13 +0200265#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200266#define USART3_BASE U(0x4000F000)
267#define UART4_BASE U(0x40010000)
268#define UART5_BASE U(0x40011000)
269#define USART6_BASE U(0x44003000)
270#define UART7_BASE U(0x40018000)
271#define UART8_BASE U(0x40019000)
Yann Gautier038bff22019-01-17 19:17:47 +0100272
273/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100274#define STM32MP_DEBUG_USART_BASE UART4_BASE
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100275#if STM32MP13
276/* UART4 on HSI@64MHz, TX on GPIOF12 Alternate 8 (Disco board) */
277#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
278#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOD_BASE
279#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_S_AHB4ENSETR
280#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_S_AHB4ENSETR_GPIODEN
281#define DEBUG_UART_TX_GPIO_PORT 6
282#define DEBUG_UART_TX_GPIO_ALTERNATE 8
283#define DEBUG_UART_TX_CLKSRC_REG RCC_UART4CKSELR
284#define DEBUG_UART_TX_CLKSRC RCC_UART4CKSELR_HSI
285#endif /* STM32MP13 */
286#if STM32MP15
Yann Gautier038bff22019-01-17 19:17:47 +0100287/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100288#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100289#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
290#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
291#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
292#define DEBUG_UART_TX_GPIO_PORT 11
293#define DEBUG_UART_TX_GPIO_ALTERNATE 6
294#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
295#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100296#endif /* STM32MP15 */
Yann Gautier038bff22019-01-17 19:17:47 +0100297#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
298#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier5c84e742020-09-14 17:21:59 +0200299#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
300#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200301
302/*******************************************************************************
Etienne Carrieree96162e2020-04-10 11:32:54 +0200303 * STM32MP1 ETZPC
304 ******************************************************************************/
305#define STM32MP1_ETZPC_BASE U(0x5C007000)
306
307/* ETZPC TZMA IDs */
308#define STM32MP1_ETZPC_TZMA_ROM U(0)
309#define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
310
311#define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
312
313/* ETZPC DECPROT IDs */
314#define STM32MP1_ETZPC_STGENC_ID 0
315#define STM32MP1_ETZPC_BKPSRAM_ID 1
316#define STM32MP1_ETZPC_IWDG1_ID 2
317#define STM32MP1_ETZPC_USART1_ID 3
318#define STM32MP1_ETZPC_SPI6_ID 4
319#define STM32MP1_ETZPC_I2C4_ID 5
320#define STM32MP1_ETZPC_RNG1_ID 7
321#define STM32MP1_ETZPC_HASH1_ID 8
322#define STM32MP1_ETZPC_CRYP1_ID 9
323#define STM32MP1_ETZPC_DDRCTRL_ID 10
324#define STM32MP1_ETZPC_DDRPHYC_ID 11
325#define STM32MP1_ETZPC_I2C6_ID 12
326#define STM32MP1_ETZPC_SEC_ID_LIMIT 13
327
328#define STM32MP1_ETZPC_TIM2_ID 16
329#define STM32MP1_ETZPC_TIM3_ID 17
330#define STM32MP1_ETZPC_TIM4_ID 18
331#define STM32MP1_ETZPC_TIM5_ID 19
332#define STM32MP1_ETZPC_TIM6_ID 20
333#define STM32MP1_ETZPC_TIM7_ID 21
334#define STM32MP1_ETZPC_TIM12_ID 22
335#define STM32MP1_ETZPC_TIM13_ID 23
336#define STM32MP1_ETZPC_TIM14_ID 24
337#define STM32MP1_ETZPC_LPTIM1_ID 25
338#define STM32MP1_ETZPC_WWDG1_ID 26
339#define STM32MP1_ETZPC_SPI2_ID 27
340#define STM32MP1_ETZPC_SPI3_ID 28
341#define STM32MP1_ETZPC_SPDIFRX_ID 29
342#define STM32MP1_ETZPC_USART2_ID 30
343#define STM32MP1_ETZPC_USART3_ID 31
344#define STM32MP1_ETZPC_UART4_ID 32
345#define STM32MP1_ETZPC_UART5_ID 33
346#define STM32MP1_ETZPC_I2C1_ID 34
347#define STM32MP1_ETZPC_I2C2_ID 35
348#define STM32MP1_ETZPC_I2C3_ID 36
349#define STM32MP1_ETZPC_I2C5_ID 37
350#define STM32MP1_ETZPC_CEC_ID 38
351#define STM32MP1_ETZPC_DAC_ID 39
352#define STM32MP1_ETZPC_UART7_ID 40
353#define STM32MP1_ETZPC_UART8_ID 41
354#define STM32MP1_ETZPC_MDIOS_ID 44
355#define STM32MP1_ETZPC_TIM1_ID 48
356#define STM32MP1_ETZPC_TIM8_ID 49
357#define STM32MP1_ETZPC_USART6_ID 51
358#define STM32MP1_ETZPC_SPI1_ID 52
359#define STM32MP1_ETZPC_SPI4_ID 53
360#define STM32MP1_ETZPC_TIM15_ID 54
361#define STM32MP1_ETZPC_TIM16_ID 55
362#define STM32MP1_ETZPC_TIM17_ID 56
363#define STM32MP1_ETZPC_SPI5_ID 57
364#define STM32MP1_ETZPC_SAI1_ID 58
365#define STM32MP1_ETZPC_SAI2_ID 59
366#define STM32MP1_ETZPC_SAI3_ID 60
367#define STM32MP1_ETZPC_DFSDM_ID 61
368#define STM32MP1_ETZPC_TT_FDCAN_ID 62
369#define STM32MP1_ETZPC_LPTIM2_ID 64
370#define STM32MP1_ETZPC_LPTIM3_ID 65
371#define STM32MP1_ETZPC_LPTIM4_ID 66
372#define STM32MP1_ETZPC_LPTIM5_ID 67
373#define STM32MP1_ETZPC_SAI4_ID 68
374#define STM32MP1_ETZPC_VREFBUF_ID 69
375#define STM32MP1_ETZPC_DCMI_ID 70
376#define STM32MP1_ETZPC_CRC2_ID 71
377#define STM32MP1_ETZPC_ADC_ID 72
378#define STM32MP1_ETZPC_HASH2_ID 73
379#define STM32MP1_ETZPC_RNG2_ID 74
380#define STM32MP1_ETZPC_CRYP2_ID 75
381#define STM32MP1_ETZPC_SRAM1_ID 80
382#define STM32MP1_ETZPC_SRAM2_ID 81
383#define STM32MP1_ETZPC_SRAM3_ID 82
384#define STM32MP1_ETZPC_SRAM4_ID 83
385#define STM32MP1_ETZPC_RETRAM_ID 84
386#define STM32MP1_ETZPC_OTG_ID 85
387#define STM32MP1_ETZPC_SDMMC3_ID 86
388#define STM32MP1_ETZPC_DLYBSD3_ID 87
389#define STM32MP1_ETZPC_DMA1_ID 88
390#define STM32MP1_ETZPC_DMA2_ID 89
391#define STM32MP1_ETZPC_DMAMUX_ID 90
392#define STM32MP1_ETZPC_FMC_ID 91
393#define STM32MP1_ETZPC_QSPI_ID 92
394#define STM32MP1_ETZPC_DLYBQ_ID 93
395#define STM32MP1_ETZPC_ETH_ID 94
396#define STM32MP1_ETZPC_RSV_ID 95
397
398#define STM32MP_ETZPC_MAX_ID 96
399
400/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200401 * STM32MP1 TZC (TZ400)
402 ******************************************************************************/
403#define STM32MP1_TZC_BASE U(0x5C006000)
404
Yann Gautier256c6b92020-10-21 18:15:12 +0200405#if STM32MP13
406#define STM32MP1_FILTER_BIT_ALL TZC_400_REGION_ATTR_FILTER_BIT(0)
407#endif
408#if STM32MP15
Yann Gautier2f974232020-09-17 12:25:05 +0200409#define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
410 TZC_400_REGION_ATTR_FILTER_BIT(1))
Yann Gautier256c6b92020-10-21 18:15:12 +0200411#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200412
413/*******************************************************************************
414 * STM32MP1 SDMMC
415 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100416#define STM32MP_SDMMC1_BASE U(0x58005000)
417#define STM32MP_SDMMC2_BASE U(0x58007000)
418#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200419
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200420/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100421 * STM32MP1 BSEC / OTP
422 ******************************************************************************/
423#define STM32MP1_OTP_MAX_ID 0x5FU
424#define STM32MP1_UPPER_OTP_START 0x20U
425
426#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
427
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100428/* OTP labels */
429#define CFG0_OTP "cfg0_otp"
430#define PART_NUMBER_OTP "part_number_otp"
Yann Gautier16188f32020-02-12 15:38:34 +0100431#if STM32MP15
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100432#define PACKAGE_OTP "package_otp"
Yann Gautier16188f32020-02-12 15:38:34 +0100433#endif
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100434#define HW2_OTP "hw2_otp"
Yann Gautierbde43da2021-08-18 15:03:40 +0200435#if STM32MP13
436#define NAND_OTP "cfg9_otp"
437#define NAND2_OTP "cfg10_otp"
438#endif
439#if STM32MP15
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100440#define NAND_OTP "nand_otp"
Yann Gautierbde43da2021-08-18 15:03:40 +0200441#endif
Yann Gautier5c1dab32019-04-17 15:12:58 +0200442#define MONOTONIC_OTP "monotonic_otp"
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100443#define UID_OTP "uid_otp"
Lionel Debieve13a668d2022-10-05 16:47:03 +0200444#define PKH_OTP "pkh_otp"
Lionel Debieve5adcd502022-10-05 16:51:12 +0200445#define ENCKEY_OTP "enckey_otp"
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100446#define BOARD_ID_OTP "board_id"
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100447
448/* OTP mask */
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100449/* CFG0 */
Nicolas Le Bayon34cbf232020-11-26 09:57:09 +0100450#if STM32MP13
451#define CFG0_OTP_MODE_MASK GENMASK_32(9, 0)
452#define CFG0_OTP_MODE_SHIFT 0
453#define CFG0_OPEN_DEVICE 0x17U
454#define CFG0_CLOSED_DEVICE 0x3FU
455#define CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN 0x17FU
456#define CFG0_CLOSED_DEVICE_NO_JTAG 0x3FFU
457#endif
458#if STM32MP15
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100459#define CFG0_CLOSED_DEVICE BIT(6)
Nicolas Le Bayon34cbf232020-11-26 09:57:09 +0100460#endif
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100461
Yann Gautierc7374052019-06-04 18:02:37 +0200462/* PART NUMBER */
Yann Gautier16188f32020-02-12 15:38:34 +0100463#if STM32MP13
464#define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0)
465#endif
466#if STM32MP15
Yann Gautierc7374052019-06-04 18:02:37 +0200467#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
Yann Gautier16188f32020-02-12 15:38:34 +0100468#endif
Yann Gautierc7374052019-06-04 18:02:37 +0200469#define PART_NUMBER_OTP_PART_SHIFT 0
470
471/* PACKAGE */
Yann Gautier16188f32020-02-12 15:38:34 +0100472#if STM32MP15
Yann Gautierc7374052019-06-04 18:02:37 +0200473#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
474#define PACKAGE_OTP_PKG_SHIFT 27
Yann Gautier16188f32020-02-12 15:38:34 +0100475#endif
Yann Gautierc7374052019-06-04 18:02:37 +0200476
Yann Gautier091eab52019-06-04 18:06:34 +0200477/* IWDG OTP */
478#define HW2_OTP_IWDG_HW_POS U(3)
479#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
480#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
481
Yann Gautier3edc7c32019-05-20 19:17:08 +0200482/* HW2 OTP */
483#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
484
Lionel Debieve402a46b2019-11-04 12:28:15 +0100485/* NAND OTP */
486/* NAND parameter storage flag */
487#define NAND_PARAM_STORED_IN_OTP BIT(31)
488
489/* NAND page size in bytes */
490#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
491#define NAND_PAGE_SIZE_SHIFT 29
492#define NAND_PAGE_SIZE_2K U(0)
493#define NAND_PAGE_SIZE_4K U(1)
494#define NAND_PAGE_SIZE_8K U(2)
495
496/* NAND block size in pages */
497#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
498#define NAND_BLOCK_SIZE_SHIFT 27
499#define NAND_BLOCK_SIZE_64_PAGES U(0)
500#define NAND_BLOCK_SIZE_128_PAGES U(1)
501#define NAND_BLOCK_SIZE_256_PAGES U(2)
502
Yann Gautierbde43da2021-08-18 15:03:40 +0200503/* NAND number of block (in unit of 256 blocks) */
Lionel Debieve402a46b2019-11-04 12:28:15 +0100504#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
505#define NAND_BLOCK_NB_SHIFT 19
506#define NAND_BLOCK_NB_UNIT U(256)
507
508/* NAND bus width in bits */
509#define NAND_WIDTH_MASK BIT(18)
510#define NAND_WIDTH_SHIFT 18
511
512/* NAND number of ECC bits per 512 bytes */
513#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
514#define NAND_ECC_BIT_NB_SHIFT 15
515#define NAND_ECC_BIT_NB_UNSET U(0)
516#define NAND_ECC_BIT_NB_1_BITS U(1)
517#define NAND_ECC_BIT_NB_4_BITS U(2)
518#define NAND_ECC_BIT_NB_8_BITS U(3)
519#define NAND_ECC_ON_DIE U(4)
520
Lionel Debieve186b0462019-09-24 18:30:12 +0200521/* NAND number of planes */
522#define NAND_PLANE_BIT_NB_MASK BIT(14)
523
Yann Gautierbde43da2021-08-18 15:03:40 +0200524/* NAND2 OTP */
525#define NAND2_PAGE_SIZE_SHIFT 16
526
527/* NAND2 config distribution */
528#define NAND2_CONFIG_DISTRIB BIT(0)
529#define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
530#define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
531
Yann Gautier5c1dab32019-04-17 15:12:58 +0200532/* MONOTONIC OTP */
533#define MAX_MONOTONIC_VALUE 32
534
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200535/* UID OTP */
536#define UID_WORD_NB U(3)
537
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100538/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200539 * STM32MP1 TAMP
540 ******************************************************************************/
541#define TAMP_BASE U(0x5C00A000)
542#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
Yann Gautier8402c292022-06-29 17:03:36 +0200543#define TAMP_BKP_REG_CLK RTCAPB
Lionel Debieve13a668d2022-10-05 16:47:03 +0200544#define TAMP_COUNTR U(0x40)
Yann Gautier41934662018-07-20 11:36:05 +0200545
Julius Werner53456fc2019-07-09 13:49:11 -0700546#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
Nicolas Toromanoffbb82b1b2022-02-09 12:26:31 +0100547static inline uintptr_t tamp_bkpr(uint32_t idx)
Yann Gautier41934662018-07-20 11:36:05 +0200548{
549 return TAMP_BKP_REGISTER_BASE + (idx << 2);
550}
551#endif
552
553/*******************************************************************************
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200554 * STM32MP1 USB
555 ******************************************************************************/
556#define USB_OTG_BASE U(0x49000000)
557
558/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200559 * STM32MP1 DDRCTRL
560 ******************************************************************************/
561#define DDRCTRL_BASE U(0x5A003000)
562
563/*******************************************************************************
564 * STM32MP1 DDRPHYC
565 ******************************************************************************/
566#define DDRPHYC_BASE U(0x5A004000)
567
568/*******************************************************************************
Yann Gautier091eab52019-06-04 18:06:34 +0200569 * STM32MP1 IWDG
570 ******************************************************************************/
571#define IWDG_MAX_INSTANCE U(2)
572#define IWDG1_INST U(0)
573#define IWDG2_INST U(1)
574
575#define IWDG1_BASE U(0x5C003000)
576#define IWDG2_BASE U(0x5A002000)
577
578/*******************************************************************************
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200579 * Miscellaneous STM32MP1 peripherals base address
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200580 ******************************************************************************/
Yann Gautiera18f61b2020-05-05 17:58:40 +0200581#define BSEC_BASE U(0x5C005000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100582#if STM32MP13
583#define CRYP_BASE U(0x54002000)
584#endif
585#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200586#define CRYP1_BASE U(0x54001000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100587#endif
Yann Gautier091eab52019-06-04 18:06:34 +0200588#define DBGMCU_BASE U(0x50081000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100589#if STM32MP13
590#define HASH_BASE U(0x54003000)
591#endif
592#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200593#define HASH1_BASE U(0x54002000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100594#endif
595#if STM32MP13
596#define I2C3_BASE U(0x4C004000)
597#define I2C4_BASE U(0x4C005000)
598#define I2C5_BASE U(0x4C006000)
599#endif
600#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200601#define I2C4_BASE U(0x5C002000)
602#define I2C6_BASE U(0x5c009000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100603#endif
604#if STM32MP13
605#define RNG_BASE U(0x54004000)
606#endif
607#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200608#define RNG1_BASE U(0x54003000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100609#endif
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200610#define RTC_BASE U(0x5c004000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100611#if STM32MP13
612#define SPI4_BASE U(0x4C002000)
613#define SPI5_BASE U(0x4C003000)
614#endif
615#if STM32MP15
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200616#define SPI6_BASE U(0x5c001000)
Yann Gautier434fa2d2021-03-23 15:25:04 +0100617#endif
Yann Gautiera18f61b2020-05-05 17:58:40 +0200618#define STGEN_BASE U(0x5c008000)
619#define SYSCFG_BASE U(0x50020000)
Yann Gautier091eab52019-06-04 18:06:34 +0200620
621/*******************************************************************************
Yann Gautier434fa2d2021-03-23 15:25:04 +0100622 * STM32MP13 SAES
623 ******************************************************************************/
624#define SAES_BASE U(0x54005000)
625
626/*******************************************************************************
627 * STM32MP13 PKA
628 ******************************************************************************/
629#define PKA_BASE U(0x54006000)
630
631/*******************************************************************************
Yann Gautierb1279e72021-12-15 13:16:15 +0100632 * REGULATORS
633 ******************************************************************************/
634/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
635#define PLAT_NB_RDEVS U(19)
Lionel Debieve84cbde32021-04-15 08:27:28 +0200636/* 2 FIXED */
Pascal Pailletff2b34c2022-03-17 17:20:22 +0100637#define PLAT_NB_FIXED_REGUS U(2)
Yann Gautierb1279e72021-12-15 13:16:15 +0100638
639/*******************************************************************************
Yann Gautier4d429472019-02-14 11:15:20 +0100640 * Device Tree defines
641 ******************************************************************************/
Nicolas Le Bayon01087912021-01-12 18:18:27 +0100642#if STM32MP13
Patrick Delaunay67bcec82022-02-16 15:45:44 +0100643#define DT_BSEC_COMPAT "st,stm32mp13-bsec"
Nicolas Le Bayon01087912021-01-12 18:18:27 +0100644#define DT_DDR_COMPAT "st,stm32mp13-ddr"
645#endif
646#if STM32MP15
Patrick Delaunay67bcec82022-02-16 15:45:44 +0100647#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
Nicolas Le Bayon8ce825f2021-05-18 10:01:30 +0200648#define DT_DDR_COMPAT "st,stm32mp1-ddr"
Nicolas Le Bayon01087912021-01-12 18:18:27 +0100649#endif
Yann Gautier091eab52019-06-04 18:06:34 +0200650#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
Yann Gautier4ede20a2020-09-18 15:04:14 +0200651#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100652#if STM32MP13
653#define DT_RCC_CLK_COMPAT "st,stm32mp13-rcc"
654#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp13-rcc-secure"
655#endif
656#if STM32MP15
Yann Gautier4d429472019-02-14 11:15:20 +0100657#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
Lionel Debieve3c0fbfe2020-12-15 10:35:59 +0100658#define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
Gabriel Fernandez1308d752020-03-11 11:30:34 +0100659#endif
Yann Gautier006bb512021-01-20 14:10:57 +0100660#define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
Patrick Delaunay98e028c2022-04-14 11:15:43 +0200661#define DT_UART_COMPAT "st,stm32h7-uart"
Yann Gautier4d429472019-02-14 11:15:20 +0100662
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200663#endif /* STM32MP1_DEF_H */