Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 1 | /* |
Vishnu Banavath | 2b651ea | 2022-01-19 18:43:12 +0000 | [diff] [blame] | 2 | * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | |
| 9 | #include <common/bl_common.h> |
| 10 | |
Satish Kumar | aa4a3af | 2021-10-27 16:31:04 +0100 | [diff] [blame] | 11 | #include <drivers/generic_delay_timer.h> |
| 12 | #include <drivers/io/io_storage.h> |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 13 | #include <plat/common/platform.h> |
Satish Kumar | aa4a3af | 2021-10-27 16:31:04 +0100 | [diff] [blame] | 14 | #include <plat/arm/common/arm_fconf_getter.h> |
| 15 | #include <plat/arm/common/arm_fconf_io_storage.h> |
| 16 | #include <plat/arm/common/plat_arm.h> |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 17 | #include <platform_def.h> |
| 18 | |
| 19 | /* |
| 20 | * Table of regions to map using the MMU. |
| 21 | * Replace or extend the below regions as required |
| 22 | */ |
| 23 | |
| 24 | const mmap_region_t plat_arm_mmap[] = { |
| 25 | ARM_MAP_SHARED_RAM, |
| 26 | ARM_MAP_NS_SHARED_RAM, |
| 27 | ARM_MAP_NS_DRAM1, |
Vishnu Banavath | 2b651ea | 2022-01-19 18:43:12 +0000 | [diff] [blame] | 28 | CORSTONE1000_MAP_DEVICE, |
| 29 | CORSTONE1000_EXTERNAL_FLASH, |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 30 | {0} |
| 31 | }; |
| 32 | |
Satish Kumar | aa4a3af | 2021-10-27 16:31:04 +0100 | [diff] [blame] | 33 | static void set_fip_image_source(void) |
| 34 | { |
| 35 | const struct plat_io_policy *policy; |
| 36 | /* |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 37 | * metadata for firmware update is written at 0x0000 offset of the flash. |
| 38 | * PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted. |
| 39 | * As per firmware update spec, at a given point of time, only one bank |
| 40 | * is active. This means, TF-A should boot from the same bank as TF-M. |
| 41 | */ |
Satish Kumar | aa4a3af | 2021-10-27 16:31:04 +0100 | [diff] [blame] | 42 | volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG); |
David Vincze | bfdb726 | 2022-03-03 14:35:51 +0100 | [diff] [blame] | 43 | |
Satish Kumar | aa4a3af | 2021-10-27 16:31:04 +0100 | [diff] [blame] | 44 | if (*boot_bank_flag > 1) { |
| 45 | VERBOSE("Boot_bank is set higher than possible values"); |
| 46 | } |
| 47 | |
| 48 | VERBOSE("Boot bank flag = %u.\n\r", *boot_bank_flag); |
| 49 | |
| 50 | policy = FCONF_GET_PROPERTY(arm, io_policies, FIP_IMAGE_ID); |
| 51 | |
| 52 | assert(policy != NULL); |
| 53 | assert(policy->image_spec != 0UL); |
| 54 | |
| 55 | io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec; |
| 56 | |
| 57 | if ((*boot_bank_flag) == 0) { |
| 58 | VERBOSE("Booting from bank 0: fip offset = 0x%lx\n\r", |
| 59 | PLAT_ARM_FIP_BASE_BANK0); |
| 60 | spec->offset = PLAT_ARM_FIP_BASE_BANK0; |
| 61 | } else { |
| 62 | VERBOSE("Booting from bank 1: fip offset = 0x%lx\n\r", |
| 63 | PLAT_ARM_FIP_BASE_BANK1); |
| 64 | spec->offset = PLAT_ARM_FIP_BASE_BANK1; |
| 65 | } |
| 66 | } |
| 67 | |
| 68 | void bl2_platform_setup(void) |
| 69 | { |
| 70 | arm_bl2_platform_setup(); |
| 71 | /* |
| 72 | * Identify the start address of the FIP by reading the boot |
| 73 | * index flag from the flash. |
| 74 | */ |
| 75 | set_fip_image_source(); |
| 76 | } |
| 77 | |
Vishnu Banavath | 2b651ea | 2022-01-19 18:43:12 +0000 | [diff] [blame] | 78 | /* corstone1000 only has one always-on power domain and there |
Abdellatif El Khlifi | ad9b8e5 | 2021-04-21 17:20:43 +0100 | [diff] [blame] | 79 | * is no power control present |
| 80 | */ |
| 81 | void __init plat_arm_pwrc_setup(void) |
| 82 | { |
| 83 | } |
| 84 | |
| 85 | unsigned int plat_get_syscnt_freq2(void) |
| 86 | { |
| 87 | /* Returning the Generic Timer Frequency */ |
| 88 | return SYS_COUNTER_FREQ_IN_TICKS; |
| 89 | } |
| 90 | |
| 91 | |
| 92 | /* |
| 93 | * Helper function to initialize ARM interconnect driver. |
| 94 | */ |
| 95 | void plat_arm_interconnect_init(void) |
| 96 | { |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * Helper function to place current master into coherency |
| 101 | */ |
| 102 | void plat_arm_interconnect_enter_coherency(void) |
| 103 | { |
| 104 | } |
| 105 | |
| 106 | /* |
| 107 | * Helper function to remove current master from coherency |
| 108 | */ |
| 109 | void plat_arm_interconnect_exit_coherency(void) |
| 110 | { |
| 111 | } |
| 112 | |
| 113 | /* |
| 114 | * This function is invoked during Mbed TLS library initialisation to get a heap |
| 115 | * The function simply returns the default allocated heap. |
| 116 | */ |
| 117 | |
| 118 | #if TRUSTED_BOARD_BOOT |
| 119 | int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) |
| 120 | { |
| 121 | assert(heap_addr != NULL); |
| 122 | assert(heap_size != NULL); |
| 123 | |
| 124 | return arm_get_mbedtls_heap(heap_addr, heap_size); |
| 125 | } |
| 126 | #endif |