blob: 719c39063778fb21be05096cfa8183ca6d74d9e1 [file] [log] [blame]
Jacky Bai9a6f62f2019-11-25 14:43:26 +08001/*
Jacky Bai95ec94c2020-04-13 17:44:50 +08002 * Copyright 2019-2023 NXP
Jacky Bai9a6f62f2019-11-25 14:43:26 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef DRAM_H
8#define DRAM_H
9
10#include <assert.h>
11
12#include <arch_helpers.h>
13#include <lib/utils_def.h>
14
15#include <ddrc.h>
16#include <platform_def.h>
17
18#define DDRC_LPDDR4 BIT(5)
19#define DDRC_DDR4 BIT(4)
20#define DDRC_DDR3L BIT(0)
21#define DDR_TYPE_MASK U(0x3f)
22#define ACTIVE_RANK_MASK U(0x3)
Jacky Bai95ec94c2020-04-13 17:44:50 +080023#define DDRC_ACTIVE_ONE_RANK U(0x1)
24#define DDRC_ACTIVE_TWO_RANK U(0x2)
Jacky Bai9a6f62f2019-11-25 14:43:26 +080025
Jacky Baie2507bb2021-12-20 17:56:08 +080026#define MR12 U(12)
27#define MR14 U(14)
28
Jacky Baiff820ba2020-09-08 09:55:59 +080029#define MAX_FSP_NUM U(3)
30
Jacky Bai9a6f62f2019-11-25 14:43:26 +080031/* reg & config param */
32struct dram_cfg_param {
33 unsigned int reg;
34 unsigned int val;
35};
36
37struct dram_timing_info {
38 /* umctl2 config */
39 struct dram_cfg_param *ddrc_cfg;
40 unsigned int ddrc_cfg_num;
41 /* ddrphy config */
42 struct dram_cfg_param *ddrphy_cfg;
43 unsigned int ddrphy_cfg_num;
44 /* ddr fsp train info */
45 struct dram_fsp_msg *fsp_msg;
46 unsigned int fsp_msg_num;
47 /* ddr phy trained CSR */
48 struct dram_cfg_param *ddrphy_trained_csr;
49 unsigned int ddrphy_trained_csr_num;
50 /* ddr phy PIE */
51 struct dram_cfg_param *ddrphy_pie;
52 unsigned int ddrphy_pie_num;
53 /* initialized fsp table */
54 unsigned int fsp_table[4];
55};
56
57struct dram_info {
58 int dram_type;
59 unsigned int num_rank;
Jacky Baid746daa12019-11-25 13:19:37 +080060 uint32_t num_fsp;
Jacky Bai9a6f62f2019-11-25 14:43:26 +080061 int current_fsp;
62 int boot_fsp;
Jacky Baid746daa12019-11-25 13:19:37 +080063 bool bypass_mode;
Jacky Bai9a6f62f2019-11-25 14:43:26 +080064 struct dram_timing_info *timing_info;
Jacky Baid746daa12019-11-25 13:19:37 +080065 /* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */
66 uint32_t mr_table[3][8];
Jacky Baidde85e02020-05-08 17:37:24 +080067 /* used for workaround for rank to rank issue */
68 uint32_t rank_setting[3][3];
Jacky Bai9a6f62f2019-11-25 14:43:26 +080069};
70
71extern struct dram_info dram_info;
72
73void dram_info_init(unsigned long dram_timing_base);
74void dram_umctl2_init(struct dram_timing_info *timing);
75void dram_phy_init(struct dram_timing_info *timing);
76
77/* dram retention */
78void dram_enter_retention(void);
79void dram_exit_retention(void);
80
Jacky Baid746daa12019-11-25 13:19:37 +080081void dram_clock_switch(unsigned int target_drate, bool bypass_mode);
82
83/* dram frequency change */
84void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index);
85void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate);
86
Jacky Bai9a6f62f2019-11-25 14:43:26 +080087#endif /* DRAM_H */